Skip to content

Lab 4: TinyRV1 Processor
Part F: Report

Lab 4 will give you experience designing, implementing, testing, and prototyping a single-cycle processor microarchitecture. The processor will implement the TinyRV1 instruction set. The instruction set manual is located here:

The lab will continue to leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, Topic 4: Combinational Building Blocks, Topic 6: Sequential Logic, Topic 7: Finite-State Machines, and Topic 8: Sequential Building Blocks. The lab will also leverage concepts from Topic 9: Instruction Set Architecture and Topic 10: Single-Cycle Processors The lab will continue to provide opportunities to leverage the three key abstraction principles: modularity, hierarchy, and regularity.

The lab includes six parts:

See canvas calendar or course schedule for all due dates.

  • Part A: Processor Components

  • Part B: TinyRV1 Processor

  • Part C: FPGA Prototype v1

    • Due the 1st FPGA week of Lab 4 during assigned lab section
    • This part will focus on prototyping the code developed in Part A+B
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: FPGA Prototype v2

    • Due the 2nd FPGA week of Lab 4 during assigned lab section
    • This part will focus on prototyping the code developed in Part A+B
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part E: TinyRV1 Assembly

    • Submit via GitHub by 11:59 PM
    • This part will include an accumulate assembly program, plus all of the assembly developed during Part C+D

  • Part F: Report

    • Due on the last day of classes at 11:59pm for all groups!
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, C, D, E, and F.

What do we do if we did not finish Part C or D or forgot to collect some data?

Students can still complete the report even they did not finish Part C or D. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part F. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Report Formatting

The lab report should start with no more than two pages of text. Students should include all figures, tables, and diagrams after these two pages in an appendix. The appendix can be as many pages as necessary. Do not interleave the text, figures, tables, and diagrams. There should be two pages of text and then the appendix with all of the text, figures, tables, and diagrams.

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

2. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2: Single-Cycle TinyRV1 Processor

  • Paragraph 1: Single-Cycle TinyRV1 Processor FPGA Area Analysis

    • Reference the chip planner diagram
    • Include 2-3 sentences discussing the area of the processor; mention the data you collected in Part D on the number of ALUTs, the number of dedicated logic registers, and the total percentage of the FPGA used by the processor
    • Explain why the number of logical registers is reasonable.
    • How does the processor quantiatively compare in terms of area to the more specialized hardware developed in early labs (e.g., the two-function calculator from lab 2 and the music player from lab 3)?

  • Paragraph 2: Single-Cycle TinyRV1 Processor FPGA Delay Analysis

    • Include 2-3 sentences referencing your annotated system and processor datapath diagram in the appendix, clearly describing where the critical path is in your processor, and discussing if this is the expected path
    • Include a sentence discussing the number of cycles required for the processor to accumulate 31 elements; clearly justify this cycle count
    • Include a sentence discussing the cycle time in nanoseconds (i.e., clock period, one over the clock frequency) for which your processor met timing
    • Include a sentence discussing the total expected execution time in nanoseconds required for the processor to accumulate 31 elements; you must use the key analytical equation from lecture (time/program = instructions/program * cycles/instruction * time/cycle)

Sec 3: Conclusion

  • This section should be one paragraph
  • Recall the lw.ai instruction discussed in lecture, which combines a load and a pointer increment into a single instruction; briefly explain how lw.ai would reduce the instruction count of your accumulate program compared to your Part E implementation (be specific about which instruction it eliminates per iteration)
  • Use the Iron Law to compute the total execution time of your accumulate program without lw.ai, using your measured instruction count and clock period from lab
  • Use the Iron Law to compute the total execution time with lw.ai, assuming it adds 1 ns to your clock period; use the reduced instruction count
  • Include a sentence drawing a quantitative conclusion: is adding lw.ai to TinyRV1 worth the cost to the clock period? What does this reveal about the tradeoffs involved in ISA and microarchitecture design?

Sec 4: Part A Revisions

  • This section is only required if your group pushed a revision for Part A
  • Include 1-2 sentences explaining the functionality issue in the original Part A submission
  • Include 1-2 sentences describing the fix implemented in the revised code

Appendix

  • Chip planner showing location of logic used to implement processor
  • RTL viewer showing complete hierarchy on left and full adder gate-level implementation on the right for processor
  • Embedded system diagram and processor datapath diagram with highlighted critical path and annotated delays
  • Oscillopscope waveform screenshot that clearly shows the SPI packets including both the SCLK and MOSI signals
  • Accumulate loop from your accumulate assembly program (you only need to include the new code you added, you do not need to include the boilerplate code that we provided for you)

3. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.