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Lab 4: TinyRV1 Processor
Part F: Report

Lab 4 will give you experience designing, implementing, testing, and prototyping a single-cycle processor microarchitecture and a specialized accelerator. The processor will implement the TinyRV1 instruction set. The instruction set manual is located here:

The lab will continue to leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, Topic 4: Combinational Building Blocks, Topic 6: Sequential Logic, Topic 7: Finite-State Machines, and Topic 8: Sequential Building Blocks. The lab will also leverage concepts from Topic 9: Instruction Set Architecture and Topic 10: Single-Cycle Processors The lab will continue to provide opportunities to leverage the three key abstraction principles: modularity, hierarchy, and regularity.

The lab includes seven parts:

  • Part A: Processor Components

    • Due 11/6 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 11/3
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 11/3

  • Part B: TinyRV1 Processor

    • Due 11/13 @ 11:59pm via GitHub
    • Students should work on Part B before, during, and after your assigned lab section during the week of 11/10

  • Part C: Accumulate Accelerator

    • Due 11/25 @ 11:59pm via GitHub
    • Students should plan to submit Part C before they leave for Thanksgiving Break

  • Part D: FPGA Prototype v1

    • Due week of 11/17 during assigned lab section
    • This part will focus on prototyping the code developed in Part A+B
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part E: FPGA Prototype v2

    • Due week of 12/1 during assigned lab section
    • This part will focus on prototyping the code developed in Part A+B+C
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part F: TinyRV1 Assembly

    • Due 12/4 @ 11:59pm via GitHub
    • This part will include all of the assembly developed during Part D+E

  • Part G: Report

    • Due on 12/8 at 11:59pm for all groups!
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, C, D, E, F, and G.

What do we do if we did not finish Part D or E or forgot to collect some data?

Students can still complete Part G even they did not finish Part D or E. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part G. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Report Formatting

The lab report should start with no more than two pages of text. Students should include all figures, tables, and diagrams after these two pages in an appendix. The appendix can be as many pages as necessary. Do not interleave the text, figures, tables, and diagrams. There should be two pages of text and then the appendix with all of the text, figures, tables, and diagrams.

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

2. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2: Single-Cycle TinyRV1 Processor

  • Paragraph 1: Accumulate Assembly Program

    • Include a sentence referencing your final accumulate assembly loop listing in the appendix
    • Include 2-3 sentences clearly describing how the accumulate assembly program works

  • Paragraph 2: Single-Cycle TinyRV1 Processor FPGA Area Analysis

    • Reference the chip planner diagram
    • Include 2-3 sentences discussing the area of the processor; mention the data you collected in Part D on the number of ALUTs, the number of dedicated logic registers, and the total percentage of the FPGA used by the processor
    • Explain why the number of logical registers is reasonable.
    • How does the processor quantiatively compare in terms of area to the more specialized hardware developed in early labs (e.g., the two-function calculator from lab 2 and the music player from lab 3)?

  • Paragraph 3: Single-Cycle TinyRV1 Processor FPGA Delay Analysis

    • Include 2-3 sentences referencing your annotated system and processor datapath diagram in the appendix, clearly describing where the critical path is in your processor, and discussing if this is the expected path
    • Include a sentence discussing the number of cycles required for the processor to accumulate 31 elements; clearly justify this cycle count
    • Include a sentence discussing the cycle time in nanoseconds (i.e., clock period, one over the clock frequency) for which your processor met timing
    • Include a sentence discussing the total expected execution time in nanoseconds required for the processor to accumulate 31 elements; you must use the key analytical equation from lecture (time/program = instructions/program * cycles/instruction * time/cycle)
    • Reference the oscilloscope screen capture which clearly shows the delay of the accumulate loop in microseconds and explain if this measurement matches the expected execution time

Sec 3: Accumulate Accelerator

  • This section should be one paragraph
  • Include a sentence referencing your datapath block diagram
  • If you used a FSM control unit, include an FSM diagram and a sentence referencing this diagram
  • Include several sentences that clearly explain how your accumulate accelerator works by describing the interaction between the datapath and control unit; be sure to clearly explain how the accelerator starts and stops and processes multiple messages
  • Use the accumulate interactive simulator to calculate the number of cycles required for the accelerator to accumulate 31 elements
  • Qualitatively estimate if your accumulate accelerator would have a similar or smaller cycle time (i.e., clock period, one over the clock frequency) compared to the processor
  • Qualitatively estimate if your accumulate accelerator would have similar or less area compared to the processor

Sec 4: Conclusion

  • This section should be one paragraph
  • Include a sentence that provides a clear area and delay comparison between using a general-purpose processor (using the quantitative data you collected in lab) vs. specialized hardware (using your rough estimates) for this accumulate kernel
  • Include a sentence that provides a clear qualitative comparison in terms of design complexity and generality between using a general-purpose processor vs. specialized hardware
  • Include a sentence that draws a high-level conclusion; how has what you have learned impact your perspective of computer engineering

Appendix

  • Chip planner showing location of logic used to implement processor
  • RTL viewer showing complete hierarchy on left and full adder gate-level implementation on the right for processor
  • Embedded system diagram and processor datapath diagram with highlighted critical path and annotated delays
  • Oscillopscope waveform screenshot that clearly shows the SPI packets including both the SCLK and MOSI signals
  • Accumulate loop from your accumulate assembly program (you only need to include the new code you added, you do not need to include the boilerplate code that we provided for you)
  • Oscilloscope waveform screenshot showing the execution time in nanoseconds of the accumulate assembly program executing on your TinyRV1 processor
  • Accumulate accelerator datapath diagram
  • Accumulate accelerator FSM diagram if appropriate

3. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.