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Lab 3: Music Player
Part B: Breadboard, FPGA, and Simulation

Lab 3 will give you experience designing, implementing, testing, and prototyping combinational and sequential logic using the Verilog hardware description language. The lab will continue to leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks but will also leverage concepts from Topic 6: Sequential Logic, Topic 7: Finite-State Machines, and Topic 8: Sequential Building Blocks. More specifically, the lab will give students experience with: latches, flip-flops, and registers; Moore and Mealy FSMs; and counters. The lab will continue to reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a music player that takes as input a song selection (via the switches) and a start song signal (via a push button). The music player will then play the chosen song by generating a square wave at appropriate note frequencies suitable for use with a piezoelectric buzzer. An idle signal is displayed using an LED so that the user knows when the player is ready to play a new song. The music player will make use of the adders and muxes from Lab 2. The song selection and the current note are both displayed using seven-segment displays from Lab 1. This lab also serves as a transition from lower-level gate-level (GL) modeling to higher-level register-transfer-level (RTL) modeling. Some of parts of your design will use explicit GL modeling, while other parts of your design will use RTL modeling. Students will have a chance to appreciate how RTL modeling can improve productivity but with less control over the final hardware implementation. The lab includes six parts:

  • Part A: Counters

    • Due 10/15 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 10/5
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 10/5

  • Part B: Breadboard, FPGA, and Simulation

    • Due week of 10/5 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part C: Music Player

    • Due 10/22 @ 11:59pm via GitHub
    • Plan to work on Part C after fall break and during the week of 10/19

  • Part D: FPGA Prototype v1

    • Due week of 10/19 during assigned lab section
    • This part will focus on prototyping the code developed in Part A
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part E: FPGA Prototype v2

    • Due week of 10/26 during assigned lab section
    • This part will focus on prototyping the code developed in Part C
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part F: Report

    • Due week of 10/26, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes that you have read and understand the course tutorials and that you have attended the discussion sections.

Here are the steps to get started:

  • Step 1. Find your lab partner
  • Step 2. Find a free workstation
  • Step 3. Ask the TAs for a lab check-off sheet and lab worksheet (use one worksheet per group, but each student needs their own check-off sheet)

You can also find a copy of the lab worksheet online here:

Throughout this handout you will need to complete lab check-off tasks. For each lab check-off task you must raise your hand and have a TA come to check-off your work. The TA will ask you the questions included as part of the lab check-off task and the assess your understanding using the following rubric: mastery; accomplished; emerging; beginning. If the TA and students together feel the students have not mastered the lab check-off task, the students are encouraged to take a few minutes and try again.

Lab Check-Off Task 1: Setup Lab Kit

The TAs will pass out an ECE 2300 Lab Kit to each group. The TAs will record the kit number on your check-off sheet. For this lab, you will receive an FPGA board, a discrete logic board, a USB-B cable, a USB-C cable, and a component box with wires. Do not do anything with the FPGA or discrete logic boards until later in the lab.

1. Simulate DLatch

We always use simulation to verify a design before prototyping the designs on the lab bench. In this section, we will use our graphical logic simulator to model both an SR latch and a D latch.

2.1. Step 1: SR Latch

Recall from lecture that an SR latch is the most basic sequential logic gate implemented using two NOR2 gates in a feedback loop.

Review your notes from lecture and fill out the following truth table for a SR latch. Use \(Q_{prev}\) if a signal depends on the previous value of Q.

S R W Q
0 0
0 1
1 0
1 1

Click on this link to launch a very simple graphical logic simulator:

Press Clear to clear the default design and then go ahead and implement the SR latch using the graphical logic simulator. You must draw the gate-level netlist so it matches the figure above. When routing a wire, you can click a grid location to crete an anchor point allowing you to create arbitrary multi-segment routes. Verify the implementation produces the correct outputs for all rows in your truth table, and all previous state values.

2.1. Step 2: D Latch

In an SR, the same signals are used to specify both what we want to remember and when we want to remember. Recall from lecture that a D latch separates these two concerns. The D input specifies what we want to remember, and the clock input specifies when we remember.

Review your notes from lecture and fill out the following truth table for a D latch. Use \(Q_{prev}\) if a signal depends on the previous value of Q.

clk D D' S R W Q
0 0
0 1
1 0
1 1

Click on this link to launch the simple graphical logic simulator in a new tab:

Press Clear to clear the default design and then go ahead and implement the D latch using the graphical logic simulator. You must draw the gate-level netlist so it matches the figure above. When routing a wire, you can click a grid location to crete an anchor point allowing you to create arbitrary multi-segment routes. Verify the implementation produces the correct outputs for all rows in your truth table, and all previous state values.

Lab Check-Off Task 2: Verify Design in Simulation

Show a TA your truth table for the SR latch. Then show the TA that your implementation produces the correct outputs. Demonstrate the set, reset, and hold modes of the SR latch. Clearly illustrate when the SR latch holds the previous value by having it hold two different values. Show a TA your truth table for the D latch. Then show the TA that your implementation produces the correct outputs. Illustrate both the transparent and the opaque phases. Clearly show when the D latch holds the previous value of the D input by having it hold two different values.

2. D Latch Breadboard Prototype

We now want to implement the D latch on the breadboard. The D latch has five gates so it is still reasonably complicated. We will take a two-step incremental design approach; each step involves planning our breadboard wiring first before implementing the wiring on the actual breadboard.

You Must Use Custom Cut Jumpers!

As with our last breadboard prototype, you should cut, strip, and bend your own jumper wires especially for jumper wires which are going a very short distance. This will make your breadboard tidy and easier to debug. Watch this video to learn how to cut, strip, and bend your own jumper wires:

You should still use the premade jumpers to connect the digital inputs to the logic gates and to connect the logic gates to the digital outputs. Please spend some time making your breadboard prototype neat and tidy!

2.1. Step 1: SR Latch

We will start by only implementing the SR latch. You must assign the digital inputs and outputs as follows:

  • Digital Input 1: S
  • Digital Input 0: R
  • Digital Output 0: Q

We need to plan our wiring before actually implementing more complicated breadboard prototypes. We will be using the breadboard diagram on the provided lab worksheet. Just as in the previous labs, you should draw lines which connect different squares together to explicitly show how you want to connect the squares on the breadboard. Do not just connect the pins of the logic gates on plan. Think carefully about which square you want to start a jump and which square you want to end a jumper.

You can route the design however you like, but think carefully about how to avoid too many crossing wires. Use as many short straight horizontal routes as you can, so you can implement these routes using custom cut jumpers. You can implement longer routes using the 4" premade jumpers. Once you have your plan, then go ahead and wire these three gates on the breadboard.

Lab Check-Off Task 3: Demonstrate SR Latch

Show a TA your breadboard plan. If your plan is incorrect or difficult to read the TAs will ask you to do it again. If your short routes on the breadboard do not use custom cut jumpers and/or are messy, then the TAs will ask you to do it again. If your routes between the logic gates and the digital inputs/outputs do not use premade jumpers, then the TAs will ask you to do it again. Explain where each of the two logic gates in the gate-level network are located in the actual combinational logic ICs. Demonstrate the set, reset, and hold modes of the SR latch. Clearly illustrate when the SR latch holds the previous value by having it hold two different values.

2.2. Step 2: D Latch

You can now remove the wires conecting the inputs S and R to the digital inputs. We will now modify the SR latch to implement a D latch. You must assign the digital inputs and outputs as follows:

  • Digital Input 1: clk
  • Digital Input 0: D
  • Digital Output 0: Q

We need to plan our wiring before actually implementing more complicated breadboard prototypes. We will be using the breadboard diagram on the provided lab worksheet. Just as in the previous labs, you should draw lines which connect different squares together to explicitly show how you want to connect the squares on the breadboard. Do not just connect the pins of the logic gates on plan. Think carefully about which square you want to start a jump and which square you want to end a jumper.

You can route the design however you like, but think carefully about how to avoid too many crossing wires. Use as many short straight horizontal routes as you can, so you can implement these routes using custom cut jumpers. You can implement longer routes using the 4" premade jumpers. Once you have your plan, then go ahead and wire these three gates on the breadboard.

Lab Check-Off Task 4: Demonstrate D Latch

Show a TA your breadboard plan. If your plan is incorrect or difficult to read the TAs will ask you to do it again. If your short routes on the breadboard do not use custom cut jumpers and/or are messy, then the TAs will ask you to do it again. If your routes between the logic gates and the digital inputs/outputs do not use premade jumpers, then the TAs will ask you to do it again. Explain where each of the logic gates in the gate-level network are located in the actual combinational logic ICs. Demonstrate the D latch by toggling the clock and data inputs. Illustrate both the transparent and the opaque phases. Clearly show when the D latch holds the previous value of the D input by having it hold two different values.

3. D Flip-Flop Breadboard Prototype

In this next part you will be prototyping a D flop-flop.

A D latch integrates two D latches: a leader latch and a follower latch. The key difference is that the clock to the leader latch is inverted with respect to the follower latch.

Team up with another group which has finished their full-adder breadboard prototype. Use the following steps to create a D flip-flop.

  • Turn off both breadboards.

  • Connect both of your breadboards to the same workstation using the USB-C cables so they have a common ground.

  • Decide which breadboard will be the leader latch and which breadboard will be follower latch. Position the leader latch to the left of the follower latch.

  • Disconnect both D and clock of the follower latch from the digital inputs.

  • Be sure to keep Q of the leader latch connected to a digital output so you can monitor the N1 node between the two latches.

  • Modify the leader latch so the clock input goes to an additioanl NOT gate first.

  • Cut a relatively long piece of wire and carefully connect Q from the leader latch to D of the follwer latch.

  • Cut a relatively long piece of wire and carefully connect clock from the leader latch to clock of the follower latch.

  • Double check your wiring.

Now turn on both boards and test that your D flip-flop is able to hold the input after the rising edge using the following steps:

  • Always start with the clock set to zero
  • Set the data to be what you want to store in the D flip-flop
  • You can toggle the data and make sure the output does not change
  • Set the clock to one and then back to zero
  • Then set the data to a new value you want to store in the D flip-flop

Lab Check-Off Task 5: Demonstrate D Flip-Flop

Show a TA your D flip-flop breadboard prototype. Clearly show that the D input only impacts the output on the rising edge by toggling the D input when the clock is low. Clearly show when the D input holds the previous value of the D input by having it hold two different values.

4. Sequential Pair/Triple Detector FPGA Prototype

Recall from Lab 1, that the output of a pair/triple detector is one if either two or three of the inputs are one, and the output should be zero otherwise. A sequential pair/triple detector adds D flip-flops to all three inputs and the outputs. Here is a gate-level network that implements a sequential pair/triple detector.

In this part, you will implement a sequential pair/triple detector FPGA prototype.

4.1. Setup Quartus Project

Click Quartus (Quartus Prime 18.1) on the desktop to start Quartus. Important: Ensure that the Quartus Version is 18.1 and not 23.1. Then, click Run the Quartus Prime software. You might need to try starting Quartus twice. Setup a new Quartus project using the New Project Wizard:

  • Directory, Name, Top-Level Entity
    • You must enter the working directory as follows with your NetID!
    • Working directory: C:\Users\netid\lab3b
    • Name of this project: lab3b
    • Name of top-level design entity: lab3b
    • Click Next
  • Directory does not exist. Do you want to create it?
    • Click yes
  • Project Type
    • Choose Empty Project
    • Click Next
  • Add Files
    • Do not add any files
    • Click Next
  • Family, Device, and Board Settings
    • Click Board tab
    • Family: Cyclone V
    • Select DE0-CV Development Board
    • Make sure Create top-level design file is checked
    • Click Next
  • EDA Tool Settings
    • Click Next
  • Summary
    • Click Finish

You must use the following steps to ensure Quartus knows your design includes RTL modeling:

  • Choose Assignments > Settings from the menu
  • Select the category Compiler Settings > Verilog HDL Input
  • Under Verilog version click SystemVerilog
  • Click OK

4.2. Implement

We need to create two new modules: a combinational pair/triple detector and a D flip-flop. To create a new file for the combinational pair/triple detector within your Quartus project:

  • Go to File -> New
  • Click on Verilog HDL File, then select OK
  • You should now see a blank Verilog file. Go to File -> Save As, and save this file as PairTripleDetector_RTL.v within your lab3b directory

In PairTripleDetector_RTL.v, define a module named PairTripleDetector_RTL that represents the gate-level network above.

module PairTripleDetector_RTL
(
  (* keep=1 *) input  logic in0,
  (* keep=1 *) input  logic in1,
  (* keep=1 *) input  logic in2,
  (* keep=1 *) output logic out
);

  assign out = /* fill in Boolean equation here */;

endmodule

Unlike before when we implemented the pair/triple detector using explicit gate-level modeling, here we will be using RTL modeling. Write the Boolean equation that directly implements pair/triple detector gate-level network using the & and | operators.

To create a new file for the D flip-flop within your Quartus project:

  • Go to File -> New
  • Click on Verilog HDL File, then select OK
  • You should now see a blank Verilog file. Go to File -> Save As, and save this file as DFF_RTL.v within your lab3b directory

In DFF_RTL.v, define a module named DFF_RTL.

module DFF_RTL
(
  (* keep=1 *) input  logic clk,
  (* keep=1 *) input  logic d,
  (* keep=1 *) output logic q
);

  ...

endmodule

Implement a D flip-flop using RTL modeling. You should use a single always_ff block.

4.3. Integrate

We can now integrate these modules into the top-level design by instantiating these modules in the DE0_CV_golden_top module. If you scroll to the bottom of the DE0_CV_golden_top.v file you will see the module does not contain any logic yet. Go ahead and instantiate four DFF_RTL modules and one PairTripleDetector_RTL within the DE0_CV_golden_top module. Wire them such that there is one D flip-flop connected to each input and one D flip-flop for the output. Connect the module to the switches and LEDs as follows:

  • The first button is for clk
  • The first switch is for in0
  • The second switch is for in1
  • The third switch is for in2
  • The first LED is for out

Lab Check-Off Task 6: Discuss Integration

Show a TA your implementation of the combinational pair/triple detector, the D flip-flop, and how you integrated them together at the top-level.

4.4. Synthesize

As always, we need to give Quartus information about our timing constraints, so that it can properly analyze the timing of our design and analyze the critical path. However, our timing constraints are more complicated now that we are using sequential logic.

  • Choose File > New from the menu
  • Click Synopsys Design Constraints File
  • Click OK
  • Enter the constraints shown below
  • Click File > Save from the menu
  • Name the file timing.sdc
  • Save the file in the lab3b directory
# Constrain paths that start at an input port and end at an output port
set_max_delay -from [all_inputs] -to [all_outputs] 20
set_min_delay -from [all_inputs] -to [all_outputs] 0

# Constrain paths that start at a flip-flop and end at a flip-flop
create_clock -name clk -period 20 [get_ports {KEY[0]}]

# Constrain paths that start at an input port and end at a flip-flop
set_input_delay  -add_delay -clock clk -max 0 [all_inputs]
set_input_delay  -add_delay -clock clk -min 0 [all_inputs]

# Constrain paths that start at a flip-flop and end at an output port
set_output_delay -add_delay -clock clk -max 0 [all_outputs]
set_output_delay -add_delay -clock clk -min 0 [all_outputs]

These constraints constrain four kinds of paths. We will discuss all of these in more detail in a later lab, but for now we will only focus on the create_clock constraint. This constraint constrains paths that start at a flip-flop and end at a flip-flop. We are constraining these paths so that they must have a maximum delay of 20ns (i.e., the clock period is a maximum of 20ns).

Now use the following steps to synthesize your design.

  • Choose Processing > Start Compilation from the menu
  • Wait 1-2 minutes for synthesis to complete

How do I fix "Verilog HDL syntax" errors?

This might be because you did not configure Quartus to use SystemVerilog! You can use the following steps to ensure Quartus knows your design includes RTL modeling:

  • Choose Assignments > Settings from the menu
  • Select the category Compiler Settings > Verilog HDL Input
  • Under Verilog version click SystemVerilog
  • Click OK

4.5. Analyze

Let's focus on just analyzing the timing (i.e., the critical path delay) of your design. Analyzing sequential timing is more complicated than analyzing combinational timing. Assume we find the critical path to be as shown below.

The critical path delay will now include three key parts:

  • Clock-to-Q Propagation Delay: This is the delay inside the D flip-flop from the rising edge of the clock to when Q changes.

  • Combinational Logic Propagation Delay: This is just the standard propagation delay through the combinational logic gates which we have seen in previous labs.

  • Setup Time: If D changes too close to the rising edge of the clock, then the D flip-flop might not be able to reliably store the new value of D. So the setup time is how long before the rising edge D must be stable to to ensure that we can reliably store the value of the D input

We will analyze timing for the Slow 1100mV 85C Model which is the default choice in the Timing Analyzer and see if we can measure all three parts.

  • Choose Tools > Timing Analyzer from the menu
  • Double-click Update Timing Netlist
  • Choose Reports > Custom Reports > Report Timing from the menu
  • Report Timing
    • Clocks - From clock: clk
    • Clocks - To clock: clk
    • Targets - From: [get_registers *]
    • Targets - To: [get_registers *]
    • Report number of paths: 100
    • Detail level: Path Only (click Set Default)
    • Click Report Timing

We will use the following conventions when analyzing the critical path based on FPGA timing reports. The FPGA timing report will have three parts:

  • The clock part of the data arrival path. This is the delay from the clock pin to the flip-flop at the start of the path. We will ignore this part in this class!

  • The data part of the data arrival path. This is the actual propagation path delay from one flip-flop to another flip-flop. This is the part you need to report on in this class!

  • The clock part of the data required path. This is the delay from the clock pin to the flip-flop at the end of the path. We will ignore this part in this class!

The following timing report illustrates these three parts:

The above image shows that you should count the delay from the start of the path until the signal leaves the initial flip-flop or register module as the clock-to-q delay (0ns in this example), and you should count the delay from when the signal enters the final flip-flop until the end of the path as the setup time (5.214ns in this example). The remaining delay is the combinational logic propagation delay (1.005ns in this example). If you select multiple cells in the Incr column and hover your mouse it will display a pop-up showing the sum of the delays along that portion of the path. Notice that the propagation path delay and the slack do not add up to the clock constraint. This is due to clock skew and clock uncertainty, which we will discuss later.

Use your timing report to annotate the sequential pair/triple detector block diagram on the provided worksheet. Your goal is to first highlight where the critical path goes through the gate-level network. Then annotate the actual delays in nanoseconds for the clock-to-q propagation delay, combinational logic propagation delay, and setup time on the gate-level network.

4.6. Configure

Now we are ready to configure the FPGA for the sequential pair/triple detector demo.

  • Choose Tools > Programmer from the menu
  • Click Hardware Setup
  • Currently selected hardware: USB-Blaster [USB-0]
  • Click Close
  • Click Start

Try changing the inputs and toggle the clock twice. The first time you toggle the clock the input data will be stored in the input flip-flops. The second time you toggle the clock the output will be stored in the output flip-flop and then you should be able to see the result using the LED. Confirm that changing the inputs without toggling the clock does not change the output (i.e., the flip-flops are holding their values).

Lab Check-Off Task 7: Demonstrate Sequential Pair/Trip Detector

Show a TA your annotated block diagram. Discuss how to measure the clock-to-q propagation delay, combinational logic propagation delay, and the setup time using the timing report. Show a TA that your pair/triple detector is correct by trying several inputs and toggling the clock appropriately. Explain what is different from this sequential pair/triple detector and the combinational pair/triple detector we prototyped in an earlier lab.

Lab Check-Off Task 8: Turn in Lab Kit

When you are finished with your demo, pack up your ECE 2300 Lab Kit. Return the FPGA board, discrete logic board, USB-B cable, USB-C cable, and component box to a TA who will then record the kit number on your check-off sheet.

5. Counters

Spend the remainder of the lab section working on the D latch, D flip-flops, multi-bit registers, equality comparators, multiplexors, and counters as described in the Lab 3A handout. Use your laptops and/or VS Code on the workstation to log into ecelinux. Your goal is to have some number of modules implemented and tested by the end of the lab section. Remember to take an incremental design approach. Do not implement all of the modules and then start testing! Implement a module, and then immediately add new directed/random tests to fully verify its functionality before moving on to the next module! Consider having one student work on the implementation while the other student works on the testing for one module and then switching roles for the next module. The TAs are here to help!

Lab Check-Off Task 9: Verify Design in Simulation

Show a TA the modules you have working by running the corresponding tests. If you do not have any modules working, at least show a TA how your implementation is coming along. Once you have finished showing a TA your progress, the TA will mark which steps are complete, and collect your check-off sheet. You do not need to complete all steps during this lab section!