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Lab 3: Music Player
Part E: Report

Lab 3 will give you experience designing, implementing, testing, and prototyping combinational and sequential logic using the Verilog hardware description language. The lab will continue to leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks but will also leverage concepts from Topic 6: Sequential Logic, Topic 7: Finite-State Machines, and Topic 8: Sequential Building Blocks. More specifically, the lab will give students experience with: latches, flip-flops, and registers; Moore and Mealy FSMs; and counters. The lab will continue to reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a music player that takes as input a song selection (via the switches) and a start song signal (via a push button). The music player will then play the chosen song by generating a square wave at appropriate note frequencies suitable for use with a piezoelectric buzzer. An idle signal is displayed using an LED so that the user knows when the player is ready to play a new song. The music player will make use of the adders and muxes from Lab 2. The song selection and the current note are both displayed using seven-segment displays from Lab 1. This lab also serves as a transition from lower-level gate-level (GL) modeling to higher-level register-transfer-level (RTL) modeling. Some of parts of your design will use explicit GL modeling, while other parts of your design will use RTL modeling. Students will have a chance to appreciate how RTL modeling can improve productivity but with less control over the final hardware implementation. The lab includes five parts:

  • Part A: Counter and Note Player

    • Due 10/19 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 10/6
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 10/6

  • Part B: Multi-Note and Music Player

    • Due 10/26 @ 11:59pm via GitHub
    • Plan to work on Part B after fall break and during the week of 10/20

  • Part C: FPGA Prototype v1

    • Due week of 10/20 during assigned lab section
    • This part will focus on prototyping the code developed in Part A
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: FPGA Prototype v2

    • Due week of 10/27 during assigned lab section
    • This part will focus on prototyping the code developed in Part B
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part E: Report

    • Due week of 10/27, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, C, and D.

What do we do if we did not finish Part C or D or forgot to collect some data?

Students can still complete Part E even they did not finish Part C or D. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part E. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Report Formatting

The lab report should start with no more than two pages of text. Students should include all figures, tables, and diagrams after these two pages in an appendix. The appendix can be as many pages as necessary. Do not interleave the text, figures, tables, and diagrams. There should be two pages of text and then the appendix with all of the text, figures, tables, and diagrams.

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

2. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2. Gate-Level Counter Design

  • This section should be one paragraph
  • Include your GL block diagram you completed in Part A in the appendix
  • Include a sentence referencing your block diagram
  • Include 3+ sentences that describe how your counter works including how it loads in new counter values and how to implements the done signal

Sec 3. Gate-Level vs RTL Design

  • Paragraph 1: Analyzing the Gate-Level Counter

    • Include the completed FPGA data table mentioned in Part C in the appendix
    • Make sure the critical path is annotated with the component delays on your GL block diagram
    • Include a sentence referencing the results in the data table
    • Include a sentence and where the critical path goes through the GL counter
    • Discuss the delay of the various components along the critical path (you must mention clock-to-q and setup time)
    • Explain why the GL counter does not meet timing and does not have any dedicated logic registers

  • Paragraph 2: Analyzing the RTL Counter

    • Include a sentence referencing your technology map screenshot
    • Discuss how the various Verilog constructs turn into specific low-level hardware in the FPGA
    • Be specific and discuss how each of these map into the technology map viewer: (1) the storage element that keeps track of the current count; (2) the storage element that keeps track of the finish value; (3) the logic that increments the count; (4) the logic that determines what should be the next stored count; (5) the logic that determines whether the counter is done
    • Discuss whether or not the number of dedicated logic registers in the RTL counter is expected
    • Be specific and count registers in your Verilog and argue why the number of dedicated logic registers is in the counter

Sec 4: Note, Multi-Note, and Music Players

  • This section should be one paragraph
  • Include the completed Note Player GL Control FSM worksheet you completed in Part A in the appendix
  • Briefly reference your simulated waveforms and your oscilloscope waveforms for your multi-note player
  • Explain what note you tried, the expected note period, the measured note period in simulation, and the measured note period using the oscilloscope
  • Briefly reference your simulated waveforms and your oscilloscope waveforms for your music player
  • Explain which song you tried, the notes you see in simulation, and the notes you see using the oscilloscope

Sec 5: Conclusion

  • This section should be one paragraph
  • Include 2-3 sentences that summarizes all of the data and analysis in this lab assignment
  • Include 2-3 sentences about the connection between RTL and GL modeling
  • Include a sentence that draws a high-level conclusion; how will what you have learned impact your design work throughout the rest of the semester?

Appendix

  • Completed note player GL countrol FSM worksheet
  • Block diagram for GL counter with highlighted critical path and annotated delays
  • FPGA data table
  • Technology map viewer for RTL counter annotated with Verilog code snippets
  • Critical path report for GL counter (1 page max, fixed width font!)
  • Critical path report for RTL counter (1 page max, fixed width font!)
  • Simulated waveform screenshot for multi-note player clearly showing note period
  • Oscilloscope waveform screenshot for multi-note player clearly showing note period
  • Simulated waveform screenshot for music player clearly showing some number of notes
  • Oscilloscope waveform screenshot for music player clearly showing some number of notes

3. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.