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Lab 2: Two-Function Calculator
Part E: Datasheets and Report

Lab 2 will give you experience designing, implementing, testing, and prototyping more complicated combinational logic using the Verilog hardware description language. This lab will primarily leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks including experience with adders, multiplexors, and multipliers. This lab will also reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a two-function calculator that takes as input two binary values and then calculates either the sum or the product of these two values. The input values and the result will be displayed on seven-segment displays using your Verilog hardware design from Lab 1. Your implementation will mostly use gate-level modeling, but you will also start to explore very simple register-transfer-level modeling. Parts of the calculator will be used in future labs. The lab includes five parts:

  • Part A: Adders and Muxes

    • Due 9/24 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/24
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 9/24

  • Part B: Breadboard and Simulation

    • Due week of 9/21 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part C: Multipliers and Calculator

    • Due 10/1 @ 11:59pm via GitHub
    • Plan to start on Part B during the week of 9/21
    • Even though Part C is due on 10/1 you still need the code ready to go before your lab section the week of 9/28!

  • Part C: FPGA Prototype

    • Due week of 9/28 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: Datasheets and Report

    • Due week of 9/28, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, C, and D.

What do we do if we did not finish Part D or forgot to collect some data?

Students can still complete Part E even they did not finish Part D. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part E. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Datasheets

There are two separate Canvas assignments: one for the datasheets and one for the report. Both must be submitted in PDF format. To export your datasheets to PDF choose File > Download > PDF then be sure to choose Export: Workbook. You must include all datasheets in the PDF to receive full credit! Your PDF should also include the final overview table, chip planers, and area vs delay plot. You must try to make sure all diagrams and screenshots are readable.

How do we download the images from the datasheet?

You can download the images from your datasheet if you want to edit them (e.g., crop them to make them more readable). To do this you need to choose File > Download > OpenDocument. Then renable the file extension from .ods to .zip and unzip this archive. You will find a Pictures folder which has all the images from the datasheets.

1.1. Interface

For all datasheets, list the ports which make up the module's interface. For each port enter the name, bit width, and whether it is an input or output port.

1.2. Functionality

For all datasheets, briefly describe the high-level functionality of the module. Do not describe the detailed implementation. Instead focus on the high-level behavior.

For the calculator prototype datasheet, describe in more detail the what the calculator does including how the overflow LED works. Be sure to explain that the calculator can only perform 2-bit by 16-bit multiplication.

1.3. Block Diagram

For the ripple-carry and carry-select adder datasheets, use the block diagram from the Lab 2D worksheet. The block diagram should be annotated with the actualy delays you found by analyzing the critical path. Make sure your block diagram is cropped and legible. Always choose Insert > Insert image in cell from the menu when adding images to the datasheet.

For the RTL adder datasheet, ideally we want a screenshot of the Technology Map Viewer. However, it is also ok to use a screenshot of the RTL Viewer or a screensshot of the Technology Map Viewer just for the critical path.

For the calculator prototype datasheet, you need to draw a block diagram of the calculator prototype. The block diagram should include the calculator, three five-bit numeric display units, input switches, input push button, seven-segment displays, and the overflow LED. You do not need to "drill down" and show what is inside the calculator or the five-bit numeric display units. You can just represent those as a box and show how they are connected to each other and to the switches, buttons, displays, and LED.

Always choose Insert > Insert image in cell from the menu when adding images to the datasheet.

1.4. Chip Planner

For all datasheets, use the cropped chip planner (just the rectangular view of the FPGA). Always choose Insert > Insert image in cell from the menu when adding images to the datasheet.

1.5. Area

For all datasheets, the number of logic gates should be the combinational ALUT usage for logic from the area report. The percent of chip used is automatically calculated for you.

1.6. Waveform

You will need to run simulations on ecelinux to collect a waveform for all three adder designs. The calculator prototype datasheet does not require a waveform.

For the ripple-carry adder, run your random test for AdderRippleCarry_16b_GL and open the resulting waveform in Surfer as follows:

% cd ${HOME}/ece2300/groupXX/build
% make AdderRippleCarry_16b_GL-test
% ./AdderRippleCarry_16b_GL-test +test-case=X +dump-vcd=waves-rc.vcd
% code waves-rc.vcd

were X is the test case number corresponding to your random tests. Display the following signals in Surfer:

  • dut.in0
  • dut.in1
  • dut.cin
  • carry out of both 8-bit ripple carry adders
  • dut.cout
  • dut.sum

Zoom in so you can see the first five additions. Do not show too much of the intial red X values. Make sure the data is shown in hexadecimal. If it is not in hexadecimal, right click on the signal and choose Format > Hexadecimal. Here is an example of a nicely formatted waveform screenshot.

Notice how the cout for both adder0 (the first 8-bit ripple-carry adder) and adder1 (the second 8-bit ripple carry adder) are displayed. The exact names in your design are likely different.

For the carry-select adder, run your random test for AdderCarrySelect_16b_GL and open the resulting waveform in Surfer. Display the following signals in Surfer:

  • dut.in0
  • dut.in1
  • dut.cin
  • carry out of all three 8-bit ripple carry adders
  • dut.cout
  • dut.sum

Zoom in so you can see the first five additions. Do not show too much of the intial red X values. Make sure the data is shown in hexadecimal. If it is not in hexadecimal, right click on the signal and choose Format > Hexadecimal.

For the RTL adder, run your random test for Adder_16b_RTL and open the resulting waveform in Surfer. Display the following signals in Surfer:

  • dut.in0
  • dut.in1
  • dut.cin
  • dut.cout
  • dut.sum

Zoom in so you can see the first five additions. Do not show too much of the intial red X values. Make sure the data is shown in hexadecimal. If it is not in hexadecimal, right click on the signal and choose Format > Hexadecimal.

Remember to always choose Insert > Insert image in cell from the menu when adding images to the datasheet.

1.7. Timing

For all datasheets, use the experiments you conducted with different timing constraints. Each experiment should list the constraint, slack, critical path delay (this is calculated for you as constraint - slack), and whether this experiment meets timing (i.e., positive slack). Find the smallest constraint which meets timing and enter the corresponding critical path delay in the True Minimum Critical Path Delay field.

For the calculator prototype datasheet, you likely only completed one experiment with a constraint of 30ns, so there may be only a single row in the Timing secgion.

1.8. Critical Path

Use the timing report for the experiment with the smallest constraint which meets timing to show the delay of every gate along the critical path.

1.9. Overview Tab

Ensure the Overview tab includes the correct data and chip planners for all four designs. Ensure the plot correctly shows the area vs delay trade-offs for the three adder designs.

2. Report

There are two separate Canvas assignments: one for the datasheets and one for the report. Both must be submitted in PDF format.

The lab report should have no more than two pages of text. There are should be no figures, tables, or diagrams in the report. All figures, tables, and diagrams will be in your datasheets. There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page.

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

All comparisons should be both qualitative and quantitative. Do not just say Design A is smaller than Design B or Design A is faster than Design B. Engineers are quantitative! A quantitative comparison means stating something like "Design A has reduces the area by XX% compared to Design B" or "Design A reduces the delay by XX% compared to Design B". Focus not just on "what" but also "why". All comparisons should also strive to explain why there is a difference!

2.1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

2.2: Testing Strategy

  • This section should be one paragraph
  • Include one sentence about the importance of a comprehensive testing strategy
  • Include 1-2 sentences about what is exhaustive testing and which modules used exhaustive testing
  • Include 2-3 sentences about what is directed testing and which modules used directed testing; why do we need directed testing? mention specific kinds of directed test cases you included
  • Include 2-3 sentences about what is random testing and which modules used random testing; why do we need random testing? mention specific kinds of random test cases you included

2.3: Comparative Analysis

  • Paragraph 1: Adder Area Comparison

    • Include a sentence referencing the area data in the datasheets for all three adder designs
    • Include 2+ sentences qualitatively and quantitatively comparing the area of the ripple-carry adder to the carry-select adder; you must quantify the difference; say one design reduces the area by XX% compared to the other design; you must explain why the area of one adder is more or less than the other adder
    • Include 2+ sentences qualitatively and quantitatively comparing the area of the RTL adder to the other two adders; you must quantify the difference; say one design reduces the area by XX% compared to the other design; you must try your best to explain why the area of the RTL adder is more or less than the other adders

  • Paragraph 2: Adder Delay Comparison

    • Include a sentence referencing the timing data in the datasheets for all three adder designs
    • Include a sentence describing where the critical path goes in detail for the ripple-carry adder by referencing the annotated block diagram and critical path sections of your datasheets
    • Include a sentence describing where the critical path goes in detail for the carry-select adder by referencing the annotated block diagram and critical path sections of your datasheets
    • Include 2+ sentences comparing the critical path delays for the ripple-carry adder and the carry-select adder; you must quantify the difference; say one design reduces the delay by XX% compared to the other design; you must explain why the delay of one adder is more or less than the other adder
    • Include 2+ sentences comparing the delay of the RTL adder to the other two adders; you must quantify the difference; say one design reduces the delay by XX% compared to the other design; you must try your best to explain why the delay of the RTL adder is more or less than the other adders

2.4: Conclusion

  • This section should be one paragraph
  • Include 2-3 sentences that summarizes all of the data and analysis in this lab assignment
  • The summary should be both qualitative and quantitative!
  • Include a sentence that draws a high-level conclusion; how will what you have learned impact your design work throughout the rest of the semester?

3. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.