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Lab 2: Two-Function Calculator
Part D: FPGA Prototype

Lab 2 will give you experience designing, implementing, testing, and prototyping more complicated combinational logic using the Verilog hardware description language. This lab will primarily leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks including experience with adders, multiplexors, and multipliers. This lab will also reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a two-function calculator that takes as input two binary values and then calculates either the sum or the product of these two values. The input values and the result will be displayed on seven-segment displays using your Verilog hardware design from Lab 1. Your implementation will mostly use gate-level modeling, but you will also start to explore very simple register-transfer-level modeling. Parts of the calculator will be used in future labs. The lab includes five parts:

  • Part A: Adders and Muxes

    • Due 9/24 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/24
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 9/24

  • Part B: Breadboard and Simulation

    • Due week of 9/21 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part C: Multipliers and Calculator

    • Due 10/1 @ 11:59pm via GitHub
    • Plan to start on Part B during the week of 9/21
    • Even though Part C is due on 10/1 you still need the code ready to go before your lab section the week of 9/28!

  • Part C: FPGA Prototype

    • Due week of 9/28 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: Datasheets and Report

    • Due week of 9/28, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes that you have read and understand the course tutorials and that you have attended the discussion sections. This handout assumes you have successfully completed Parts A+C, meaning your adders, multiplier, and two-function calculator are all working in simulation.

What do we do if Part C is not done?

We assume students have completed Part C and will have the full three hours to complete Part D. If Part C is almost done, students could try to quickly get it working but they risk not being able to complete Part D. If Part C is far from done, students may want to skip Lab Check-Off Task 2 (but make sure all of your adder implementations pass all of your tests!) and work on Lab Check-Off Tasks 3-6 first. They can work on Part C while they are witing for the FPGA tools to synthesize their adders. Once they have completed Lab Check-Off Tasks 3-6, they can try to get Part C working and then try to complete Lab Check-Off Tasks 2, 7, and 8.

Here are the steps to get started:

  • Step 1. Find your lab partner
  • Step 2. Find a free workstation
  • Step 3. Ask the TAs for a lab check-off sheet and lab worksheet (use one worksheet per group, but each student needs their own check-off sheet)

You can also find a copy of the lab worksheet online here:

For each lab check-off task you must raise your hand and have a TA come to check-off your work. The TA will ask you the questions included as part of the lab check-off task and the assess your understanding using the following rubric: mastery; accomplished; emerging; beginning. If the TA and students together feel the students have not mastered the lab check-off task, the students are encouraged to take a few minutes and try again.

When the lab handout requires you to collect data or save a screenshot, place it in the corresponding location in your group's Lab 2 datasheet. These datasheets will be used to organize important information for the modules you are evaluating in lab. We provide you a template for your datasheets here:

Create a copy of this template for your own use by choosing File > Make a copy. Share this spreadsheet with your partner so you can work together on your datasheets. You do not need to have your datasheets completely finished by the end of Part D, but you do need to have the completed and submitted on Canvas for Part E.

What do we do if the TAs are busy?

Students must maintain a sense of urgency throughout the three hour lab section. When you get to a lab check-off task, raise your hand for 2-3 minutes. If no TA is available you must keep going; if nothing else read ahead and make a plan for the next section of the lab handout. If you do nothing and wait 20-30mins with your hand raised for a TA then you will not be able to finish all of Part D. You must be strategic. Keep moving through the handout and bring over a TA when they are free to possibly look at multiple lab check-off tasks. If you are truly stuck and no TA is available, ask your neighbors. We need to all work together to make sure every student can complete Part D. There are no extensions and students cannot complete Part D at any other time except during their assigned lab section.

Lab Check-Off Task 1: Setup Lab Kit

The TAs will pass out an ECE 2300 Lab Kit to each group. The TAs will record the kit number on your check-off sheet. For this lab, you will receive the FPGA board, a USB cable, and a component box with an LED, resistor, and some wires. Use the USB cable to plug the FPGA board into the workstation.

1. Simulate Two-Function Calculator

Before starting to work on an FPGA prototype, you must make sure you have a working Verilog hardware design that has been thoroughly tested in simulation. One student should start VS Code on the workstation by finding the ECE 2300 folder and double clicking the ECE 2300 Start VS Code shortcut. Then source the setup script and make sure your individual git repository is up to date.

% source setup-ece2300.sh
% cd ${HOME}/ece2300/groupXX
% git pull
% tree

where XX is your group number. Now run all of the tests from a clean build to ensure your design is fully functional.

% cd ${HOME}/ece2300/groupXX
% trash build
% mkdir build
% cd build
% ../configure
% make check

We now need to get the files for your design from ecelinux onto the workstation. This requires multiple steps.

  • Step 1. Click Microsoft Edge on the desktop to open a web-browser on the workstation to log into GitHub and then find your repository

  • Step 2. Start PowerShell by clicking the Start menu then searching for Windows PowerShell

  • Step 3. Use the following command to change to your home directory on the workstation in the lab (where netid is your Cornell NetID)

% cd C:\Users\netid
  • Step 4. Clone your repo onto the workstation by using this command in PowerShell (where netid is your Cornell NetID, notice we are using https!):
% git clone https://github.com/cornell-ece2300/groupXX

  • Step 5. In the Connect to GitHub pop-up, click Sign in with your browser

  • Step 6. You may be asked for your GitHub username again and you may be asked to authorize the Git Credential Manager; click authorize git-ecosystem

  • Step 7. Verify that you have successfully cloned your repo by changing into your repo and using tree on the workstation:

% cd groupXX
% tree

Lab Check-Off Task 2: Verify Design in Simulation

Show a TA that your hardware designs are passing all of test benches on ecelinux.

2. Setup Quartus Project

Click Quartus (Quartus Prime 18.1) on the desktop to start Quartus. Important: Ensure that the Quartus Version is 18.1 and not 23.1. Then, click Run the Quartus Prime software. You might need to try starting Quartus twice. Setup a new Quartus project using the New Project Wizard:

  • Directory, Name, Top-Level Entity
    • You must enter the working directory as follows with your NetID!
    • Working directory: C:\Users\netid\lab2d
    • Name of this project: lab2d
    • Name of top-level design entity: lab2d
    • Click Next
  • Directory does not exist. Do you want to create it?
    • Click yes
  • Project Type
    • Choose Empty Project
    • Click Next
  • Add Files
    • Click User Libraries...
    • Click triple dots to the right of Project library name
    • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > groupXX where XX is your group number
    • Click Select Folder
    • Click Add
    • Click OK
    • Click triple dots to right of File name
    • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > groupXX > lab2 where XX is your group number
    • Shift-click on every Verilog hardware design file (do not include any files in the test or sim subdirectories)
    • Click Open
    • Click Next
  • Family, Device, and Board Settings
    • Click Board tab
    • Family: Cyclone V
    • Select DE0-CV Development Board
    • Make sure Create top-level design file is checked
    • Click Next
  • EDA Tool Settings
    • Click Next
  • Summary
    • Click Finish

There is a new setting we did not need in Lab 1! You must use the following steps to ensure Quartus knows your design includes RTL modeling:

  • Choose Assignments > Settings from the menu
  • Select the category Compiler Settings > Verilog HDL Input
  • Under Verilog version click SystemVerilog
  • Click OK

3. Synthesize and Analyze Adders

We will start by synthesizing and analyzing three different adder designs in isolation. When we say in isolation we mean that our goal is not to actually prototype these adder designs on the FPGA (e.g., demo the adders with switches and seven segment displays), but our goal is instead to perform a rigorous comparative analysis across multiple adder designs. Once we better understand the adder design space we can then select the appropriate adder for use in the final FPGA prototype.

Before starting, we want to predict the critical path for the ripple-carry and carry-select adders. Find the block diagram for the ripple carry and carry-select adders on the provided worksheet. Clearly draw your predicted critical path on each block diagram. Save these diagrams since you will be continuing to annotate them throughout the lab, and you will need to include them in your datasheets.

Lab Check-Off Task 3: Discuss Predicted Adder Critical Paths

Show a TA your block diagrams with the critical paths. Explain to the TA which design should have a shorter critical path and why. How much shorter will the critical path be?

3.1. Synthesize and Analyze Ripple-Carry Adder

We will be using a slightly different approach to synthesize and analyze the adders in isolation compared to our process in Lab 1. When pushing a hardware design through the flow in isolation, we want to let the FPGA tools automatically assign the top-level ports to the FPGA pins. This will enable the FPGA to optimize this assignment improving the overall critical path and enabling a more rigorous analysis.

To synthesize and analyze the ripple-carry adder in isolation use the following steps:

  • Find the Project Navigator pane
  • Click on Hierarchy to display the drop-down list
  • Choose Files and select the AdderRippleCarry_16b_GL.v file
  • Right click on the file and choose Select as Top-Level Entity
  • Click on Files to display the drop-down list again
  • Choose Hierarchy and confirm that AdderRippleCarry_16b_GL is shown as the only entity

As in Lab 1, we need to create a timing constraint file. As mentioned in Lab 1, the FPGA tools do not synthesize the design to just run as fast as possible. The way the FPGA tools work, is that the designer provides a timing constraint on the critical path delay, and the tools work as hard as they can (but no harder!) to meet this critical path delay constraint. When finished, the design will either "meet timing" (i.e., the actual critical path delay is less than the constraint) or "not meet timing" (i.e., the actual critical path delay is greater than the constraint).

Here are the steps to create a timing constraint file:

  • Choose File > New from the menu
  • Click Synopsys Design Constraints File
  • Click OK
  • Enter the constraints shown below
  • Click File > Save from the menu
  • Name the file timing.sdc
  • Save the file in the lab2d directory

We will use the following initial constraints:

set_max_delay -from [all_inputs] -to [all_outputs] 20
set_min_delay -from [all_inputs] -to [all_outputs] 0

These constraints tell the FPGA tools that our critical path delay constraint is 20ns and that the FPGA tools should analyze all paths from every input port to every output port.

Now use the following steps to synthesize your design.

  • Choose Processing > Start Compilation from the menu
  • Wait 1-2 minutes for synthesis to complete

How do I fix "can't open Verilog Design File" errors?

This probably means you did not setup the user library correctly, so Quartus cannot find the files you are including using the include Verilog preprocessor directive. You can use the following steps to fix this:

  • Choose Assignments > Settings from the menu
  • Select the category Libraries
  • Click triple dots to the right of Project library name
  • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > groupXX where XX is your group number
  • Click Select Folder
  • Click Add
  • Click OK
  • Choose Processing > Start Compilation from the menu to see if this fixes the issue

How do I fix "Verilog HDL syntax" errors?

This might be because there is a new setting we did not need in Lab 1! You can use the following steps to ensure Quartus knows your design includes RTL modeling:

  • Choose Assignments > Settings from the menu
  • Select the category Compiler Settings > Verilog HDL Input
  • Under Verilog version click SystemVerilog
  • Click OK

Now let's look at the RTL viewer, technology map viewer, and chip planner.

  • RTL Viewer
    • Choose Tools > Netlist Viewer > RTL Viewer from the menu
    • Drill down in the hierarchy to see the netlist for the 16-bit ripply-carry adder, the 8-bit ripple-carry adder, and the full adder
    • Does the RTL viewer match your expectations? Where would the critical path go on this diagram?
    • Choose File > Close from menu to close the RTL viewer
  • Technology Map Viewer
    • Choose Tools > Netlist Viewer > Technology Map Viewer (Post-Fitting)
    • Drill down in the hierarchy to see the implementation of the 16-bit ripply-carry adder, the 8-bit ripple-carry adder, and the full adder
    • Does the technology map viewer match your expectations? Where would the critical path go on this diagram?
    • Choose File > Close from the menu to close the technology map viewer
  • Chip Planner
    • Choose Tools > Chip Planner from the menu
    • Identify where the logic used to implement your design is located in the FPGA
    • Choose File > Close from the menu to close the chip planner

The next step is to analyze the area of your design.

  • Choose Processing -> Compilation Report from the menu
  • Under Table of Contents choose Fitter > Resource Section > Resource Usage Summary
  • Look for Combinational ALUT usage for logic to find the total number of logic gates used for your design

The final step is to analyze the timing (i.e., the critical path delay) of your design. We will analyze timing for the Slow 1100mV 85C Model which is the default choice in the Timing Analyzer.

  • Choose Tools > Timing Analyzer from the menu
  • Double-click Update Timing Netlist
  • Choose Reports > Custom Reports > Report Timing from the menu
  • Report Timing
    • From: [all_inputs]
    • To: [all_outputs]
    • Report number of paths: 100
  • Identify the propagation delay of the longest path
  • Look at the actual critical path (i.e., Data Arrival Path) which shows the longest path from one of the inputs through your design to one of the outputs

If you design meets timing, you will need to decrease the constraint 1ns at a time until it does not meet timing; alternatively, if your design does not meet timing, you will need to increase the constraint 1ns at a time until it does meet timing. We can consider the shortest critical path delay while still meeting timing as the "true minimum critical path delay". You only need to do as many experiments as required to calculate the true minimum critical path delay. So the iterative process will look like this:

  • Edit the timing constraints file to change the critical path delay constraint by one nanosecond or more
  • Choose Processing > Start Compilation from the menu
  • Wait 1-2 minutes for synthesis to complete
  • Analyze the area of your design
  • Analyze the timing of your design

You will be working to fill in the Timing section of the datasheet for the ripple-carry adder. You can save time by not generating a brand new timing report. You can instead simply use the following steps.

  • Choose Processing -> Compilation Report from the menu
  • Under Table of Contents choose Timing Analyzer > Slow 1100mV 85C Model > Setup Summary
  • The critical path delay is just the constraint minus the slack

Once you have found the minimum timing constraint which still meets timing, record the true minimum critical path delay in the Timing section of the datasheet. Record the number of logic gates (i.e., combinational ALUT usage for logic) in the Area section of the datasheet. Save a screenshot of the Chip Planner (just the rectangular view of the FPGA) using WindowsKEY+SHIFT+S for your datasheet. Use the Timing Analyzer to find the corresponding critical path. Then use the following steps to update the Critical Path section of the datasheet.

  • Select the complete Data Arrival Path, including all columns, rows, values, and netnames, and copy it to the clipboard
  • Paste the copied Data Arrival Path into the Critical Path section of your datasheet where it says paste here

Draw the actual critical path on the second block diagram for the ripple-carry adder using the timing report. Label the first four of the full adders along the critical path with their corresponding delay using the timing report (you do not need to label all of the full adders!). To determine the delay between different points along the critical path, use SHIFT-select to highly multiple cells in the Increment column of the Critical Path section of your datasheet. Then the sum will be displayed in the lower right corner of the Google spreadsheet. So you can highlight the cells in the Increment column from a full adder's carry in to it's carry out to get the total delay through that full adder. Include buffering delay between full adders as part of the delay of the full adder. Label the delay to get from the FPGA input pin to the ripple-carry adder and the delay to get from the ripple-carry adder to the FPGA output pin.

Update Datasheet for Ripple-Carry Adder

Make sure the module name, designers, group number, chip planner, area, timing, and critical path sections of your datasheet are finished. Do not copy/paste screenshots into the datasheet. Use Insert > Insert image in Cell from the menubar to insert screenshots. The block diagram in the datasheet will be the block diagram from the worksheet annotated with the actual delays. You can update the interface, functionality, block diagram, and waveform sections later as you prepare your datasheets for submission in Part E.

Lab Check-Off Task 4: Discuss Area and Delay for Ripple-Carry Adder

Show a TA the progress you have made on your datasheet for the ripple-carry adder. Use your worksheet to show a TA the actual critical path on the block diagram for the ripple-carry adder. How does the actual critical path compare to the predicted critical path? Clearly show how the delays in the Critical Path section of your datasheet correspond to the delays through the full adders in the block diagram.

3.2. Synthesize and Analyze Carry-Select Adder

Use the same process to synthesize and analyze the carry-select adder in isolation. Remember to change that hardware module to be the top-level entity using the following steps:

  • Find the Project Navigator pane
  • Click on Hierarchy to display the drop-down list
  • Choose Files and select the AdderCarrySelect_16b_GL.v file
  • Right click on the file and choose Select as Top-Level Entity
  • Click on Files to display the drop-down list again
  • Choose Hierarchy and confirm that AdderCarrySelect_16b_GL is shown as the only entity

For the carry-select adder use an initial timing constraint of 18ns.

Go through the same process of looking at the RTL Viewer, Technology Map Viewer, and the Chip Planner. Use the same process to iteratively change the critical path delay, by changing 20 in the timing constraint file to something smaller or larger to find the "true minimal critical path delay".

You will now be working to iterate and fill in the Timing section of the datasheet for the carry-select adder. Once you have found the minimum timing constraint which still meets timing, record the true minimum critical path delay in the Timing section of the datasheet. Record the number of logic gates (i.e., combinational ALUT usage for logic) in the Area section of the datasheet. Save a screenshot of the Chip Planner (just the rectangular view of the FPGA) using WindowsKEY+SHIFT+S for your datasheet. Use the Timing Analyzer to find the corresponding critical path, and save this critical path to the Critical Path section of the datasheet.

Draw the actual critical path on the block diagram for the carry-select adder using the timing report. Label the first four of the full adders and the 1-bit multiplexors along the critical path with their corresponding delay using the timing report (you do not need to label every full adder along the path!). To determine the delay between different points along the critical path, use SHIFT-select to highly multiple cells in the Increment column of the Critical Path section of your datasheet. Then the sum will be displayed in the lower right corner of the Google spreadsheet. So you can highlight the cells in the Increment column from a full adder's carry in to it's carry out to get the total delay through that full adder. Include buffering delay between full adders as part of the delay of the full adder. Label the delay to get from the FPGA input pin to the carry-select adder and the delay to get from the carry-select adder to the FPGA output pin.

Update Datasheet for Carry-Select Adder

Make sure the module name, designers, group number, chip planner, area, timing, and critical path sections of your datasheet are finished. Do not copy/paste screenshots into the datasheet. Use Insert > Insert image in Cell from the menubar to insert screenshots. The block diagram in the datasheet will be the block diagram from the worksheet annotated with the actual delays. You can update the interface, functionality, block diagram, and waveform sections later as you prepare your datasheets for submission in Part E.

Lab Check-Off Task 5: Discuss Area and Delay for Both Adders

Show a TA the progress you have made on your datasheet for the carry-select adder. Use your worksheet to show a TA the actual critical path on the block diagram for the carry-select adder. How does the actual critical path compare to the predicted critical path? Clearly show how the delays in the Critical Path section of your datasheet correspond to the delays through the full adders and 1-bit multiplexors in the block diagram. Use your experimental data to quantitatively explain to the TA the trade-offs between these two adders. Which adder is smallest? By what percentage is the area decreased? Which adder is the fastest? By what percentage is the critical path decreased? Be an engineer. Do not just say one is smaller than the other. Quantify the difference!

3.2. Synthesize and Analyze RTL Adder

Use the same process to synthesize and analyze the RTL adder in isolation. Remember to change that hardware module to be the top-level entity using the following steps:

  • Find the Project Navigator pane
  • Click on Hierarchy to display the drop-down list
  • Choose Files and select the Adder_16b_RTL.v file
  • Right click on the file and choose Select as Top-Level Entity
  • Click on Files to display the drop-down list again
  • Choose Hierarchy and confirm that Adder_16b_RTL is shown as the only entity

For the RTL adder use an initial timing constraint of 14ns.

Go through the same process of looking at the RTL Viewer, Technology Map Viewer, and the Chip Planner. Look closely at the Technology Map Viewer. Save a screenshot of the Technology Map Viewer using WindowsKEY+SHIFT+S for your datasheet. What kind of adder do the FPGA tools seem to be using?

You will now be working to iterate and fill in the Timing section of the datasheet for the RTL adder. Once you have found the minimum timing constraint which still meets timing, record the true minimum critical path delay in the Timing section of the datasheet. Record the number of logic gates (i.e., combinational ALUT usage for logic) in the Area section of the datasheet. Save a screenshot of the Chip Planner (just the rectangular view of the FPGA) using WindowsKEY+SHIFT+S for your datasheet. Use the Timing Analyzer to find the corresponding critical path. Use the Timing Analyzer to find the corresponding critical path, and save this critical path to the Critical Path section of the datasheet.

Update Datasheet for RTL Adder

Make sure the module name, designers, group number, block diagram chip planner, area, timing, and critical path sections of your datasheet are finished. Do not copy/paste screenshots into the datasheet. Use Insert > Insert image in Cell from the menubar to insert screenshots. The block diagram in the datasheet should be the screenshot of the Technology Map Viewer. You can update the interface, functionality, and waveform sections later as you prepare your datasheets for submission in Part E.

Lab Check-Off Task 6: Discuss Area and Delay for All Adders

Show a TA the screen shots of the RTL Viewer and the progress you have made on the datasheet for the RTL adder. Use the RTL Viewer screenshot to explain to the TA what kind of adder you think the FPGA tools are using to implement the RTL adder. Use your experimental data in the overview tab of the datasheets to quantitatively explain to the TA the trade-offs between all three adders. Which adder is the smallest? Which adder is the fastest? What conclusions can we draw in terms of how much effort we should spend trying to implement building blocks using a gate-level implementation as opposed to using RTL in our Verilog hardware designs?

4. Two-Function Calculator FPGA Prototype

We now have a fully verified Verilog hardware design, and we have finished a rigorous comparative analysis of the area and timing of three different adder implementations. The last step is to integrate, synthesize, and configure the FPGA with our design and demonstrate the final FPGA prototype!

4.1. Integrate

We need to change the top-level entity to be DE0_CV_golden_top.v using the following steps:

  • Find the Project Navigator pane
  • Click on Hierarchy to display the drop-down list
  • Choose Files and select the DE0_CV_golden_top.v file
  • Right click on the file and choose Select as Top-Level Entity
  • Click on Files to display the drop-down list again
  • Choose Hierarchy and confirm that DE0_CV_golden_top is shown as the only entity

The New Project Wizard creates a top-level Verilog module for us which has ports for all of the switches, LEDs, seven-segment displays, and general-purpose pins on the FPGA development board. We need to instantiate Calculator_GL in this top-level Verilog module along with three instances of DisplayOpt_GL and connect the ports.

Do not write your top-level integration from scratch!

You do not need to write the top-level integration from scratch. We provide a template a little later in this handout. Start by wiring up the breadboard, then use our template to get you started on the top-level integration.

Students are responsible for figuring out the appropriate top-level port connections to meet the following specification:

  • The left five switches are for in0
  • The right five switches are for in1
  • The two seven-segment displays on the left are for in0
  • The two seven-segment displays in the middle are for in1
  • The two seven-segment displays on the right are for the result
  • The right-most push button is for op
    • By default calculator should perform addition
    • Pressing the button should perform multiplication
  • The general-purpose pins will be used to connect to an LED on the breadboard
    • If the operation results in overflow, the LED should light up

Look carefully at the labels on the board to figure out how the switches, buttons, seven-segment displays, and the general-purpose pins correspond to ports in the top-level Verilog module. Notice that in this lab we are using the general-purpose pins and a breadboard. The general purpose pins are 36 pins on the FPGA which come out to a general-purpose connector. Here is more information about these pins from the FPGA datasheet:

We have created a small ribbon cable that connects these general-purpose pins to a breadboard. This breadboard is identical to the one we have been using on our discrete logic board. Recall that there are internal connections between many of the bredboard holes that you cannot see. These internal connections are shown below in purple, black, and red. We have already connected the power supply (3.3V) and ground (0V) pins to the long vertical strips shown in red (for 3.3V) and black (for 0V). The following figure illustrates the internal connections and how power and ground are connected.

We will be inserting an LED and a resistor into the breadboard. Here is what LEDs and resistors look like.

Recall that a light emitting diode (LED) is a light which turns on when current flows through it. If we directly connect an LED to one of the general purpose pins, then too much current might flow through it causing it to burn out. A resistor is an electrical component which restricts current (i.e., restricts the flow of charge). So we want to wire up an LED and resistor in series to limit the current flowing through the LED.

Insert the red LED and resistor from your kit as shown above. Choose a general-purpose pin (pin 1 works well) and connect it to one side of the LED using one of the wires in your kit. Connect the other side of the LED to ground using the resistor.

You are now ready to integrate the calculator. You will need to include the five-digit display from lab 1 at the top of DE0_CV_golden_top.v like this:

1
`include "lab1/DisplayOpt_GL.v"

We provide you a suitable template below for your top-level implementation below. You will need to fill in how these modules connect to the top-level ports. We also show you how to use an OR gate to determine if there is overflow.

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//----------------------------------------------------------------------
// Prepare input values
//----------------------------------------------------------------------
// We need to zero extend the five-bit value we get from the switches
// to a 16-bit value for use with the calculator. You need to connect
// in0 and in1 to the appropriate top-level ports.

wire [4:0] in0;
assign in0 = /* fill this in */;

wire [15:0] calc_in0;
assign calc_in0 = { 11'b0, in0 };

wire [4:0] in1;
assign in1 = /* fill this in */;

wire [15:0] calc_in1;
assign calc_in1 = { 11'b0, in1 };

//----------------------------------------------------------------------
// Instantiate the calculator
//----------------------------------------------------------------------
// You need to connect op to the appropriate top-level port.

wire [15:0] calc_result;

Calculator_GL calc
(
  .in0    (calc_in0),
  .in1    (calc_in1),
  .op     (/* fill this in */),
  .result (calc_result)
);

//----------------------------------------------------------------------
// Seven segment displays
//----------------------------------------------------------------------
// You need to connect the outputs of the displays to the appropriate
// top-level ports.

DisplayOpt_GL display_in0
(
  .in       (in0),
  .seg_tens (/* fill this in */),
  .seg_ones (/* fill this in */)
);

DisplayOpt_GL display_in1
(
  .in       (in1),
  .seg_tens (/* fill this in */),
  .seg_ones (/* fill this in */)
);

DisplayOpt_GL display_result
(
  .in       (calc_result[4:0]),
  .seg_tens (/* fill this in */),
  .seg_ones (/* fill this in */)
);

//----------------------------------------------------------------------
// Check for overflow
//----------------------------------------------------------------------
// Overflow occurs when any of the top 11 bits of the result are one
// (i.e., we cannot accurately display the result using just a five-bit
// display). We can detect overflow by OR'ing these top 11 bits. We
// want to indicate overflow by turning on the LED on the breadboard.
// So we just need to connect the output of the OR gate to the
// appropriate general-purpose pin.

or( /* fill this in */,
   calc_result[5],  calc_result[6],  calc_result[7],  calc_result[8],
   calc_result[9],  calc_result[10], calc_result[11], calc_result[12],
   calc_result[13], calc_result[14], calc_result[15] );

Use the following steps when you are ready to integrate the calculator.

  • Double-click on DE0_CV_golden_top
  • Instantiate the template shown above
  • Fill in the connections to the top-level ports
  • Choose File > Save from the menu

Lab Check-Off Task 7: Discuss Two-Function Calculator Integration

Show a TA your breadboard wiring and your top-level integration. Discuss how you connected the LED on the breadboard. Discuss how you connected the calculator to the various top-level ports.

4.2. Synthesize

You will need to update the timing constraint file as follows:

set_max_delay -from [all_inputs] -to [all_outputs] 40
set_min_delay -from [all_inputs] -to [all_outputs] 0

Notice we are using a generous constraint of 40ns. Then choose Processing > Start Compilation from the menu to synthesize your design. If your design does not meet timing the increase the timing constraint.

You do not need to iterate!

You do not need to iterate to find the true minimum critical path delay for the calculator prototype. We just want to prototype the calculator and thus are less concerned on finding the true minimum critical path delay. You only need to iterate if you do not meet timing at 40ns. If you meet timing at 40ns then you are done!

Open the Chip Planner to see where the calculator is located on the FPGA:

  • Choose Tools > Chip Planner from the menu
  • Identify where the logic used to implement your design is located in the FPGA
  • Choose File > Close from the menu to close the chip planner

Record the critical path delay in the Timing section of the datasheet. Record the number of logic gates (i.e., combinational ALUT usage for logic) in the Area section of the datasheet. Save a screenshot of the Chip Planner (just the rectangular view of the FPGA) using WindowsKEY+SHIFT+S for your datasheet. Use the Timing Analyzer to find the corresponding critical path, and save this critical path to the Critical Path section of the datasheet.

Update Datasheet for Calculator Prototype

Make sure the module name, designers, group number, chip planner, area, timing, and critical path sections of your datasheet are finished. You will need to draw your own block diagram of the calculator prototype. It should include the calculator, three five-bit numeric display units, input switches, input push button, seven-segment displays, and the overflow LED. You can update the interface, functionality, and block diagram sections later as you prepare your datasheets for submission in Part E.

4.3. Configure

Now we are finally ready to configure the FPGA for our calculator demo!

  • Choose Tools > Programmer from the menu
  • Click Hardware Setup
  • Currently selected hardware: USB-Blaster [USB-0]
  • Click Close
  • Click Start

Test out your calculator. Note that the specification requires that your calculator performs addition by default and only performs multiplication when the button is pressed. Consider this excerpt from the data-sheet for our FPGA boards.

Given this new information you may need to modify the template we gave you to add a logic gate to the top-level Verilog file to ensure your calculator correctly implements the specification.

Make sure your calculator functions correctly when there is overflow by adding and multiplying large numbers. Confirm the LED on your breadboard lights up; if the LED does not light up try flipping the LED around. LEDs only work in one direction.

Make sure the two-function calculator interactive simulator is working on ecelinux:

% cd ${HOME}/ece2300/groupXX/build
% make calculator-sim
% ./calculator-sim +in0-switches=00100 +in1-switches=00011 +button=0
% ./calculator-sim +in0-switches=00100 +in1-switches=00011 +button=1

Lab Check-Off Task 8: Demonstrate the Two-Function Calculator

First, show a TA the progress you have made on your datasheet for the calculator prototype. Then, show a TA the two-function calculator interactive simulator. The TA will give you two decimal numbers. You should first determine their unsigned binary representation, then determine what the correct unsigned binary output would be if we added these two numbers together, and finally determine what the correct unsigned output should be if we multiplied these two numbers together. Once you know these values, then use the two-function interactive simulator to verify your work. Then use the FPGA prototype to confirm it also outputs the correct decimal representation. The TA will give you additional decimal numbers which cause overflow. Your calculator must display the digits in the correct locations and perform addition by default and multiplication when the button is pressed.

Lab Check-Off Task 9: Turn in Lab Kit

When you are finished with your demo, pack up your ECE 2300 Lab Kit. Put the LED and wires back in the component box. Return the FPGA board, USB cable, and component box to a TA who will then record the kit number on your check-off sheet, initial the final check-off, and then collect your check-off sheet.