Lab 2: Two-Function Calculator
Part B: Breadboard and Simulation

Lab 2 will give you experience designing, implementing, testing, and prototyping more complicated combinational logic using the Verilog hardware description language. This lab will primarily leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks including experience with adders, multiplexors, and multipliers. This lab will also reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a two-function calculator that takes as input two binary values and then calculates either the sum or the product of these two values. The input values and the result will be displayed on seven-segment displays using your Verilog hardware design from Lab 1. Your implementation will mostly use gate-level modeling, but you will also start to explore very simple register-transfer-level modeling. Parts of the calculator will be used in future labs. The lab includes five parts:

• Part A: Adders and Muxes

  • Due 9/24 @ 11:59pm via GitHub
  • Students should work on Part A before, during, and after your assigned lab section during the week of 9/24
  • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 9/24

• Part B: Breadboard and Simulation

  • Due week of 9/21 during assigned lab section
  • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

• Part C: Multipliers and Calculator

  • Due 10/1 @ 11:59pm via GitHub
  • Plan to start on Part B during the week of 9/21
  • Even though Part C is due on 10/1 you still need the code ready to go before your lab section the week of 9/28!

• Part C: FPGA Prototype

  • Due week of 9/28 during assigned lab section
  • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

• Part D: Report and Datasheets

  • Due week of 9/28, three days after lab section @ 11:59pm via Canvas
  • Post-lab survey on Canvas is due at the same time as the report

This handout assumes that you have read and understand the course tutorials and that you have attended the discussion sections.

Here are the steps to get started:

• Step 1. Find your lab partner
• Step 2. Find a free workstation
• Step 3. Ask the TAs for a lab check-off sheet and lab worksheet (use one worksheet per group, but each student needs their own check-off sheet)

You can also find a copy of the lab worksheet online here:

• https://www.csl.cornell.edu/courses/ece2300/handouts/ece2300-lab2b-worksheet.pdf

Throughout this handout you will need to complete lab check-off tasks. For each lab check-off task you must raise your hand and have a TA come to check-off your work. The TA will ask you the questions included as part of the lab check-off task and the assess your understanding using the following rubric: mastery; accomplished; emerging; beginning. If the TA and students together feel the students have not mastered the lab check-off task, the students are encouraged to take a few minutes and try again.

Lab Check-Off Task 1: Setup Lab Kit

The TAs will pass out an ECE 2300 Lab Kit to each group. The TAs will record the kit number on your check-off sheet. For this lab, you will receive a discrete logic board, a USB-C cable, a box of wire, and a component box with jumper wires and a wire cutter/stripper. Do not do anything with the discrete logic boards until later in the lab.

1. Simulate Full Adder

Recall from lecture that a full adder adds three one-bit numbers to produce a two-bit output (i.e., the sum bit and the carry out). This is the interface for the module:

Review your notes from lecture and fill out the following truth table for a full adder on the provided lab worksheet. Make sure you completely understand this truth table before continuing.

in0	in1	cin	cout	sum
0	0	0
0	0	1
0	1	0
0	1	1
1	0	0
1	0	1
1	1	0
1	1	1

We showed in lecture how to implement this truth table as a gate-level network.

Spend minute confirming that this gate-level network does indeed implement the truth table above.

We always use simulation to verify a design before prototyping the designs on the lab bench. In the discussion section, we used both a graphical logic simulator which is a good for verifying small breadboard prototypes. Click on this link to launch a very simple graphical logic simulator:

• https://www.csl.cornell.edu/courses/ece2300/apps/logic-sketch

Press Clear to clear the default design and then go ahead and implement the full-adder using the graphical logic simulator. You must draw the gate-level netlist so it matches the figure above. You can press F to flip a device and R to rotate a device. We recommend placing the inputs first, then placing the XOR2 gates, and then connecting the inputs to the XOR2 gates. Then you can connect the AND gates to these vertical wires so you gate-level netlist matches the figure above. Verify the implementation produces the correct outputs for all rows in your truth table.

Lab Check-Off Task 2: Verify Design in Simulation

Show a TA your truth table and that your full adder implementation produces the correct outputs for all eight possible inputs and show the TA your waveforms. Be prepared to explain the purpose of the carry in and carry out.

2. Full Adder Breadboard Prototype

We now want to implement the full adder on the breadboard. The full adder has seven gates so it is more complicated than the pair/triple detector you prototyped in lab 1. When wiring your full adder breadboard prototype, you must assign the digital inputs and outputs as follows:

• Digital Input 2: in0
• Digital Input 1: in1
• Digital Input 0: cin
• Digital Output 1: cout
• Digital Output 0: sum

We will take a three-step incremental design approach; each step involves planning our breadboard wiring first before implementing the wiring on the actual breadboard.

You Must Use Custom Cut Jumpers!

We will be wiring up our breadboard differently from past lab sections. Instead of only using the premade 4" and 6" jumpers, you should cut, strip, and bend your own jumper wires especially for jumper wires which are going a very short distance. This will make your breadboard tidy and easier to debug. Watch this video to learn how to cut, strip, and bend your own jumper wires:

• https://vod.video.cornell.edu/media/t/1_iqeoungq

You should still use the premade jumpers to connect the digital inputs to the logic gates and to connect the logic gates to the digital outputs. Please spend some time making your breadboard prototype neat and tidy!

2.1. Step 1: Partial Carry Logic

We will start by only implementing the first three gates of the carry logic.

We need to plan our wiring before actually implementing more complicated breadboard prototypes. We will be using the breadboard diagram on the provided lab worksheet. You should draw lines which connect different squares together to explicitly show how you want to connect the squares on the breadboard. Do not just connect the pins of the logic gates on plan. For example, here is an incorrect breadboard plan for the first three gates of the carry logic.

This incorrect breadboard plan shows the connectivity between gates but does not explicitly show which squares to insert the jumpers. Here is a correct breadboard plan for the first three gates of the carry logic.

Here we can use three short custom cut jumpers for the horizontal routes, three 4" premade jumpers to connect the logic gates to the digital inputs, and a final 4" premade jumper to connect the logic gates to the digital output.

You can route the design however you like, but think carefully about how to avoid too many crossing wires. Use as many short straight horizontal routes as you can, so you can implement these routes using custom cut jumpers. You can implement longer routes using the 4" premade jumpers. Once you have your plan, then go ahead and wire these three gates on the breadboard.

Lab Check-Off Task 3: Demonstrate Partial Carry Logic

Show a TA your breadboard plan. If your plan is incorrect or difficult to read the TAs will ask you to do it again. If your short routes on the breadboard do not use custom cut jumpers and/or are messy, then the TAs will ask you to do it again. If your routes between the logic gates and the digital inputs/outputs do not use premade jumpers, then the TAs will ask you to do it again. Explain where each of the three logic gates in the gate-level network are located in the actual combinational logic ICs. Demonstrate that the output is one only when in0 and in1 are one OR when in0 and cin are one.

2.2. Step 2: Carry Logic

You can now remove the wire connecting the partial carry logic to the digital output. The next step is to finish the carry logic by adding one more AND2 gate and one more OR2 gate.

Copy your breadboard diagram from step 1 to the second breadboard plan on the provided lab worksheet. Then add routes for the rest of the carry logic. Keep your drawing neat and tidy. Once you have your plan, then go ahead and wire these two additional gates on the breadboard. Use custom cut jumpers for short routes, and use 4" premade jumpers for longer routes.

Lab Check-Off Task 4: Demonstrate Carry Logic

Show a TA your updated breadboard plan. If your plan is incorrect or difficult to read the TAs will ask you to do it again. If your short routes on the breadboard do not use custom cut jumpers and/or are messy, then the TAs will ask you to do it again. If your routes between the logic gates and the digital inputs/outputs do not use premade jumpers, then the TAs will ask you to do it again. Explain where each of the XOR2 gates in the gate-level network are located in the actual combinational logic ICs. Demonstrate that breadboard prototype now fully implements the carry out as described by your truth table.

2.3. Step 3: Sum Logic

The final step is to implement the sum logic by adding two XOR2 gates.

Copy your breadboard diagram from step 2 to the third breadboard plan on the provided lab worksheet. Then add routes for the rest of the carry logic. Keep your drawing neat and tidy. Once you have your plan, then go ahead and wire these two additional gates on the breadboard. Use custom cut jumpers for short routes, and use 4" premade jumpers for longer routes.

Lab Check-Off Task 5: Demonstrate Full Adder

Show a TA your updated breadboard plan. If your plan is incorrect or difficult to read the TAs will ask you to do it again. If your short routes on the breadboard do not use custom cut jumpers and/or are messy, then the TAs will ask you to do it again. If your routes between the logic gates and the digital inputs/outputs do not use premade jumpers, then the TAs will ask you to do it again. Explain where each of the XOR2 gates in the gate-level network are located in the actual combinational logic ICs. Demonstrate that breadboard prototype now fully implements the full adder as described by your truth table.

3. Ripple Carry Adder Breadboard Prototype

In this next part you will be prototyping a two-bit ripple carry adder. This is the interface:

Review your notes from lecture and fill out the following truth table for the two-bit adder on the provided lab worksheet. Assume cin is always zero. carry0 is the carry out of bit0. Make sure you completely understand this truth table before continuing.

in0	in1	carry0	cout	sum
00	00	0	0	00
00	01
...
11	10
11	11

A ripple-carry ripple-carry adder chains together full adders to implement a multi-bit binary adder. For example, we can chain two full adders together to implement a two-bit binary adder.

Team up with another group which has finished their full-adder breadboard prototype. Use the following steps to create a two-bit ripple carry adder:.

• Turn off both breadboards.

• Connect both of your breadboards to the same workstation using the USB-C cables so they have a common ground.

• Decide which breadboard will be fa1 and which breadboard will be fa0. Position the fa1 to the left of the fa0.

• Disconnect the carry in of fa1 from the digital input.

• Cut a relatively long piece of wire and carefully connect the carry out from fa0 to the carry-in of fa1.

• Double check your wiring.

Now turn on the both boards and try all 16 possible inputs from the truth table to confirm that the cout and sum values are correct.

Lab Check-Off Task 6: Demonstrate Ripple-Carry Adder

Show a TA your ripple carry adder breadboard prototype. The TA will give you two numbers to add together. Use your breadboard prototype to add these numbers and confirm that the output is correct. The TA will ask you to trace the likely critical path on the breadboards from the in0 of fa0 to the carry out of fa1.

Lab Check-Off Task 7: Turn in Lab Kit

When you are finished with your demo, pack up your ECE 2300 Lab Kit. Throw away your custom jumpers (the next group will make their own!). Return the discrete logic board, USB-C cable box of wire, and component box with jumper wires and a wire cutter/stripper to a TA who will then record the kit number on your check-off sheet.

4. Adders and Muxes

Spend the remainder of the lab section working on your adders and muxes as described in the Lab 2A handout. Use your laptops and/or VS Code on the workstation to log into ecelinux. Your goal is to have some number of modules implemented and tested by the end of the lab section. Remember to take an incremental design approach. Do not implement all of the modules and then start testing! Implement a module, and then immediately add new directed/random tests to fully verify its functionality before moving on to the next module! Consider having one student work on the implementation while the other student works on the testing for one module and then switching roles for the next module. The TAs are here to help!

Lab Check-Off Task 8: Verify Design in Simulation

Show a TA the modules you have working by running the corresponding tests. If you do not have any modules working, at least show a TA how your implementation is coming along. Once you have finished showing a TA your progress, the TA will mark which steps are complete, and collect your check-off sheet. You do not need to complete all steps during this lab section!