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Lab 2: Two-Function Calculator
Part D: Report

Lab 2 will give you experience designing, implementing, testing, and prototyping more complicated combinational logic using the Verilog hardware description language. This lab will primarily leverage concepts from Topic 2: Combinational Logic, Topic 3: Boolean Algebra, and Topic 4: Combinational Building Blocks including experience with adders, multiplexors, and multipliers. This lab will also reinforce three key abstraction principles: modularity, hierarchy, and regularity.

You will be implementing a two-function calculator that takes as input two binary values and then calculates either the sum or the product of these two values. The input values and the result will be displayed on seven-segment displays using your Verilog hardware design from Lab 1. Your implementation will mostly use gate-level modeling, but you will also start to explore very simple register-transfer-level modeling. Parts of the calculator will be used in future labs. The lab includes four parts:

  • Part A: Adders and Muxes

    • Due 9/25 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/22
    • Pre-lab survey on Canvas is (roughly) due by end of lab section during the week of 9/22

  • Part B: Multipliers and Calculator

    • Due 10/2 @ 11:59pm via GitHub
    • Plan to start on Part B during the week of 9/22
    • Even though Part B is due on 10/2 you still need the code ready to go before your lab section the week of 9/29!

  • Part C: FPGA Prototype

    • Due week of 9/29 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: Report

    • Due week of 9/29, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, and C.

What do we do if we did not finish Part C or forgot to collect some data?

Students can still complete Part D even they did not finish Part C. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part D. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Report Formatting

The lab report should start with no more than two pages of text. Students should include all figures, tables, and diagrams after these two pages in an appendix. The appendix can be as many pages as necessary. Do not interleave the text, figures, tables, and diagrams. There should be two pages of text and then the appendix with all of the text, figures, tables, and diagrams.

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

2. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2: Testing Strategy

  • This section should be one paragraph
  • Include one sentence about the importance of a comprehensive testing strategy
  • Include 1-2 sentences about what is exhaustive testing and which modules used exhaustive testing
  • Include 2-3 sentences about what is directed testing and which modules used directed testing; why do we need directed testing? mention specific kinds of directed test cases you included
  • Include 2-3 sentences about what is random testing and which modules used random testing; why do we need directed testing? mention specific kinds of random test cases you included

Sec 3: Comparative Analysis

  • Paragraph 1: Adder Area Comparison

    • Include the FPGA data table mentioned in Part C in the appendix
    • Include a sentence referencing the area data in the FPGA data table for all three adder designs
    • Include 1-2 sentences comparing the area of the ripple-carry adder to the carry-select adder; you must explain why the area of one adder is more or less than the other adder
    • Include 1-2 sentences comparing the area of the RTL adder to the other two adders; you must try your best to explain why the area of the RTL adder is more or less than the other adders

  • Paragraph 2: Adder Delay Comparison

    • Include a sentence referencing the delay data in the FPGA data table for all three adder designs
    • Include a sentence describing where the critical path goes in detail for the ripple-carry adder by referencing your timing report and your annotated block diagram
    • Include a sentence describing where the critical path goes in detail for the carry-select adder by referencing your timing report and your annotated block diagram
    • Include 1-2 sentences comparing the critical path delays for the ripple-carry adder and the carry-select adder; you must explain why the delay of one adder is more or less than the other adder
    • Include 1-2 sentences comparing the delay of the RTL adder to the other two adders; you must try your best to explain why the delay of the RTL adder is more or less than the other adders

Sec 4: Conclusion

  • This section should be one paragraph
  • Include 2-3 sentences that summarizes all of the data and analysis in this lab assignment
  • Include a sentence that draws a high-level conclusion; how will what you have learned impact your design work throughout the rest of the semester?

Appendix

  • FPGA Data Table
  • Block diagram for ripple-carry adder with highlighted critical path and annotated delays
  • Block diagram for carry-select adder with highlighted critical path and annotated delays
  • RTL Viewer for RTL adder
  • Critical Path Diagram Located in Technology Map Viewer for RTL Adder
  • Chip planner for calculator with logic highlighted
  • Critical path report for ripple-carry adder (1 page max, fixed width font!)
  • Critical path report for carry-select adder (1 page max, fixed width font!)
  • Critical path report for RTL adder (1 page max, fixed width font!)