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Lab 1: Five-Bit Numeric Display
Part E: Report

Lab 1 is designed to give you experience designing, implementing, testing, and prototyping a simple Verilog hardware design. This lab will primarily leverage concepts from Topic 2: Combinational Logic and Topic 3: Boolean Algebra.

You will be implementing a five-bit numeric display that takes as input a five-bit binary value and displays this value as a decimal number using two seven-segment displays. Your implementation will exclusively use combinational logic gates. This five-bit numeric display will be reused extensively across all of the remaining labs. The lab includes five parts:

  • Part A: Unoptimized and Optimized Display

    • Must be completed individually
    • Due 9/13 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/7

  • Part B: Breadboard and FPGA Primer

    • Done with randomly assigned partner
    • Due week of 9/7 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part C: Build System

    • Must be completed individually
    • Due 9/17 @ 11:59pm via GitHub
    • Students should work on Part C before, during, and after your assigned lab section during the week of 9/14

  • Part D: FPGA Prototype

    • Done with randomly assigned partner
    • Due week of 9/14 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part E: Report

    • Done with same partner as in Part D
    • Due week of 9/14, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed Parts A, B, C, and D.

Is acceptable for students in the same group to look at each other's code?

Since Part A and C are meant to be done alone, the course collaboration policy means students cannot look at each other's code, but obviously students will need to look at each other's code to complete Part E. So this is an exception to the course collaboration policy. Students in the same group can look at each other's code in the process of completing Part E, but students should not copy each other's code in the process of completing a revision or preparing to submit Part C. Please make sure the code you submit accurately represents your own understanding.

What do we do if we did not finish Part D or forgot to collect some data?

Students can still complete Part E even they did not finish Part D. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part E. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Report Formatting

The lab report should have no more than two pages of text. Attach each student's Part A worksheet to the end of the report as an appendix (i.e., your worksheets do not count towards the two-page limit).

Make sure your datasheets are complete and well formatted since they are considered part of your report. This means you should make sure all screen captures are reasonably sized in your datasheet!

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

2. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2: Optimizations

  • This section should be one paragraph
  • Choose one student's code to discuss in this section; it does not need to be the same code you uses for your analysis in Section 3
  • Include 2-3 sentences describing your Karnaugh map simplifications
  • Include a sentence describing why the result of your Karnaugh maps should hopefully result in a more optimized implementation
  • If you think your Karnaugh map implementation will actually be less optimized explain why

Sec 3: Comparative Analysis

  • Paragraph 1: Verilog Area Comparison

    • For this analysis, use the same code you are used in Part D
    • Count the number of logic gates in your unoptimized Verilog implementation and include a sentence discussing this count
    • Count the numer of logic gates in your optimized Verilog implementation and include a sentence discussing this count
    • Include 2-3 sentences comparing the number of logic gates in the two Verilog implementations
    • Does the optimized design use fewer logic gates?
    • Should we count two logic gates with different number of inputs as having equivalent area?

  • Paragraph 2: FPGA Area Comparison

    • Include a sentence referencing the area data in the datasheets
    • Include a sentence comparing the area of the unoptimized vs optimized designs using the data in the datasheets
    • Include a sentence relating this FPGA comparison to your comparison based purely on your Verilog gate counts

  • Paragraph 3: FPGA Delay Comparison

    • Include a 1-2 sentences referencing the timing data in the datasheets
    • Include a sentence describing where the critical path goes through the design (at a high-level) for both the unoptimized and optimized designs
    • Include a sentence comparing the critical path delay of the unoptimized vs optimized designs using the datasheets
    • Include a sentence relating this FPGA comparison to your comparison based purely on counting gates in the Verilog source code

Sec 4: Conclusion

  • This section should be one paragraph
  • Include 2-3 sentences that summarizes all of the data and analysis in this lab assignment
  • Include a sentence that draws a high-level conclusion; how will what you have learned impact your design work throughout the rest of the semester?

Appendix

  • Attach each student's Part A worksheet to the end of the report. The Part worksheets include the truth tables and Karnaugh maps.

3. Datasheet

You should refer to your datasheets throughout your report, and these datasheets will be assessed as part of your report. You should submit two datasheets:

  • Unoptimized Display
  • Optimized Display

Each datasheet should include six sections:

  1. Timing
  2. Area
  3. Chip Planer
  4. Block Diagram
  5. Waveform
  6. Critical Path

4. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.