Skip to content

Lab 1: Five-Bit Numeric Display
Part D: Report

Lab 1 is a warmup designed to give you experience designing, implementing, testing, and prototyping a simple Verilog hardware design. This lab will primarily leverage concepts from Topic 2: Combinational Logic and Topic 3: Boolean Algebra.

You will be implementing a five-bit numeric display that takes as input a five-bit binary value and displays this value as a decimal number using two seven-segment displays. Your implementation will exclusively use combinational logic gates. This five-bit numeric display will be reused extensively across all of the remaining labs. The lab includes four parts:

  • Part A: Unoptimized Code and Testing

    • Must be completed individually
    • Due 9/11 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/8

  • Part B: Optimized Code and Testing

    • Must be completed individually
    • Due 9/18 @ 11:59pm via GitHub
    • Plan to start on Part B during the week of 9/8
    • Even though Part B is due on 9/18 you still need the code ready to go before your lab section the week of 9/15!

  • Part C: FPGA Analysis and Prototyping

    • Done with randomly assigned partner
    • Due week of 9/15 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: Report

    • Done with same partner as in Part C
    • Due week of 9/15, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes both students have successfully completed all of previous parts of the lab.

What do we do if we did not finish Part C or forgot to collect some data?

Students can still complete Part D even they did not finish Part C. Students can use MS Remote Desktop to log into ecelinux and run Quartus. They can then analyze their design using Quartus including collecting data about area and timing as well as capturing various screenshots. Students will obviously not be able to configure the FPGA but they can still collect any data they need to complete Part D. See Tutorial 0 to learn more about how to use MS Remote desktop to log into ecelinux and run Quartus.

1. Verilog Area and Timing Modeling

Before starting the lab report, pick one student's code and create a Verilog data table using this template:

Count the number of gates with 1 input, 2 inputs, 3 inputs, etc in your Verilog source files and enter those numbers in the tables. The DisplayUnit includes one instance of the BinaryToBinCodedDec module and two instances of the BinaryToSevenSeg module, so the number of gates in the DisplayUnit is the number of gates in the BinaryToBinCodedDec module plus twice the number of gates in the BinaryToSevenSeg module. The provided template uses a very simple area model where the area of a gate is equal to the number of inputs to that gate.

Try to estimate where the critical path will go just based on the Verilog gate-level netlist. Keep in mind gates with more inputs are slower than gates with fewer inputs. Count the number of gates with 1 input, 2 inputs, 3 inputs, etc in your Verilog source files on that critical path and enter those numbers in the tables below. We can estimate the critical path through the DisplayUnopt_GL as the sum of the critical paths through the BinaryToBinCodedDec and BinaryToSevenSeg. The provided template uses a very simple constant delay model where the delay of a gate is equal to the number of inputs to that gate.

This data should enable you to make a very simplistic estimate of the total area and critical path delay of the unoptimized and optimized designs. Note that you cannot directly compare the area/delay estimated using your simple Verilog area/delay model to the area/delay reported by the FPGA tools; these are completely different ways to estimate area/delay. However, you can relate the two comparisions when using the same methodology: is design A better than design B when using the Verilog area/delay model but then design A is worse than design B based on the FPGA tools? or maybe design A and B are similar when using the Verilog area/delay model but they are different when using the FPGA tools? So while directly comparing numbers from your simple Verilog area/delay model and the area/delay reported by the FPGA tools is not possible, it is possible to discuss if the comparisons using the same model are similar or different.

2. Report Formatting

The lab report should start with no more than two pages of text. Students should include all figures, tables, and diagrams after these two pages in an appendix. The appendix can be as many pages as necessary. Do not interleave the text, figures, tables, and diagrams. There should be two pages of text and then the appendix with all of the text, figures, tables, and diagrams.

There are no restrictions on font size, margins, or line spacing, but please make sure your report is readable. We recommend using 10pt Times or 10pt Palintino with 0.75in to 1in margins. Please make sure you include a title, your names, and your NetIDs at the top of the first page. Do not include a title page. The report must be submitted in PDF format.

3. Report Outline

The lab report must include the following numbered sections. Please number your sections and use these specific titles. Please follow the guidelines on the number of paragraphs, the content of each paragraph, and which figures/tables to include. Some paragraphs might just be 2-3 sentences.

Sec 1: Introduction

  • This section should be one paragraph
  • Include 2-3 sentences explaining what the lab involves
  • Include one sentence explaining the purpose of this lab (why are students doing this lab?)
  • Include one sentence explicitly connecting the lab to one or more lecture topics; be specific on which lecture topics this lab reinforces with experiential learning

Sec 2: Optimizations

  • This section should be one paragraph
  • Choose one student's code to discuss in this section
  • Include a figure in the appendix showing all seven Karnaugh maps you used for your optimizations
  • Include 2-3 sentences describing your Karnaugh map simplifications
  • Include a sentence describing why the result of your Karnaugh maps should hopefully result in a more optimized implementation
  • If you think your Karnaugh map implementation will actually be less optimized explain why

Sec 3: Comparative Analysis

  • Paragraph 1: Verilog Comparison

    • Include the Verilog data table mentioned above in the appendix
    • Include the RTL Viewer screenshots for both the unoptimized and optimized designs in the appendix
    • Include a sentence referencing the Verilog data table
    • Include a sentence comparing the total area of the unoptimized vs optimized designs using the simple Verilog area model
    • Include a sentence comparing the total delay of the unoptimized vs optimized designs using the simple Verilog delay model
    • Include 2-3 sentences comparing and contrasting the unoptimized vs optimized designs based just on the original Verilog
    • Include a sentence discussing the RTL Viewer screenshots

  • Paragraph 2: FPGA Area Comparison

    • Include the FPGA data table in the appendix
    • Include a sentence referencing the area data in the FPGA data table
    • Include a sentence comparing the area of the unoptimized vs optimized designs using the FPGA area data
    • Include a sentence relating this FPGA comparison to your comparison based purely on the simple Verilog area model

  • Paragraph 3: FPGA Delay Comparison

    • Include the critical path screenshots for both the unoptimized and optimized design in the appendix
    • Include a sentence referencing the delay data in the FPGA data table
    • Include a sentence describing where the critical path goes through the design (at a high-level) for both the unoptimized and optimized designs
    • Include a sentence comparing the critical path delay of the unoptimized vs optimized designs using the FPGA delay data
    • Include a sentence relating this FPGA comparison to your comparison based purely on the simple Verilog delay model

Sec 4: Conclusion

  • This section should be one paragraph
  • Include 2-3 sentences that summarizes all of the data and analysis in this lab assignment
  • Include a sentence that draws a high-level conclusion; how will what you have learned impact your design work throughout the rest of the semester?

Appendix

  • Figure showing seven Karnaugh maps
  • Verilog data table
  • Screenshot of RTL Viewer for unoptimized design
  • Screenshot of RTL Viewer for optimized design
  • FPGA data table
  • Screenshot of critical path for unoptimized design
  • Screenshot of critical path for optimized design

4. Post-Lab Survey

Once you have finished all parts of this lab, complete the post-lab survey which is on Canvas. The post-lab survey includes questions on AI usage and workload distribution. The survey is due at the same time as the report. A student will not receive a grade for the lab unless the post-lab survey is completed.