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Lab 1: Five-Bit Numeric Display
Part C: FPGA Prototype

Lab 1 is a warmup designed to give you experience designing, implementing, testing, and prototyping a simple Verilog hardware design. This lab will primarily leverage concepts from Topic 2: Combinational Logic and Topic 3: Boolean Algebra.

You will be implementing a five-bit numeric display that takes as input a five-bit binary value and displays this value as a decimal number using two seven-segment displays. Your implementation will exclusively use combinational logic gates. This five-bit numeric display will be reused extensively across all of the remaining labs. The lab includes four parts:

  • Part A: Unoptimized Code and Testing

    • Must be completed individually
    • Due 9/11 @ 11:59pm via GitHub
    • Students should work on Part A before, during, and after your assigned lab section during the week of 9/8

  • Part B: Optimized Code and Testing

    • Must be completed individually
    • Due 9/18 @ 11:59pm via GitHub
    • Plan to start on Part B during the week of 9/8
    • Even though Part B is due on 9/18 you still need the code ready to go before your lab section the week of 9/15!

  • Part C: FPGA Analysis and Prototyping

    • Done with randomly assigned partner
    • Due week of 9/15 during assigned lab section
    • Even though completed with a partner, every student must turn in their own paper check-off sheet in their lab section!

  • Part D: Report

    • Done with same partner as in Part C
    • Due week of 9/15, three days after lab section @ 11:59pm via Canvas
    • Post-lab survey on Canvas is due at the same time as the report

This handout assumes that you have read and understand the course tutorials and that you have attended the discussion sections. This handout assumes both students have successfully completed Parts A+B. For Parts A+B, students worked individually, so for Part C, you should choose one student's code to use for the FPGA prototype. Obviously only choose code which is fully functional, but also choose whichever student's implementation of BinaryToSevenSegOpt_GL seems to be more aggressively optimized.

What do we do if both students have not sucessfully completed Part A and Part B?

Students can still complete Part C even if both students have not completed Parts A+B. At least one of the two students in a group needs to have optimized a minimum of three outputs in the binary-to-seven-segment converter and have this partially optimized design passing their tests along with the optimized five-digit numeric display. If this minimum requirement is satisfied do not use your lab section to optimize more of the design or get both student's code working. Focus on completing the FPGA prototype.

Here are the steps to get started:

  • Step 1. Check Canvas for your randomly assigned lab partner (click on People, then Groups, then search for your name to find your group named ECE 2300: Lab 1 Group XX where XX is your group number)
  • Step 2. Find your randomly assigned lab partner
  • Step 3. Find a free workstation
  • Step 4. Ask the TAs for a lab check-off sheet (each student needs their own check-off sheet)

Throughout this handout you will see two kinds tasks: lab report tasks and lab check-off tasks.

For each lab report task you must take some notes, save a screenshot, and/or record some data for your lab report. Students can start working on their lab report during their lab session, but will likely need to continue working on their lab report after the lab session. The lab report is due on Canvas at 11:59pm three days after your assigned lab section.

For each lab check-off task you must raise your hand and have a TA come to check-off your work. The TA will ask you the questions included as part of the lab check-off task and the assess your understanding using the following rubric: mastery; accomplished; emerging; beginning. If the TA and students together feel the students have not mastered the lab check-off task, the students are encouraged to take a few minutes and try again.

What do we do if the TAs are busy?

Students must maintain a sense of urgency throughout the three hour lab section. When you get to a lab check-off task, raise your hand for 2-3 minutes. If no TA is available you must keep going; if nothing else read ahead and make a plan for the next section of the lab handout. If you do nothing and wait 20-30mins with your hand raised for a TA then you will not be able to finish all of Part C. You must be strategic. Keep moving through the handout and bring over a TA when they are free to possibly look at multiple lab check-off tasks. If you are truly stuck and no TA is available, ask your neighbors. We need to all work together to make sure every student can complete Part C. There are no extensions and students cannot complete Part C at any other time except during their assigned lab section.

Lab Check-Off Task 1: Setup FPGA Board

Request an FPGA board from the TAs. The TAs will record the board number on your check-off sheet. Use the power cord to plug the FPGA board into an outlet, and use the USB cable to plug the FPGA board into the workstation.

1. Simulation of Five-Bit Numeric Display

Before starting to work on an FPGA prototype, you must make sure you have a working Verilog hardware design that has been thoroughly tested in simulation. The student whose code will be used for Part C should start VS Code on the workstation, log into a specific ecelinux server, source the setup script, and make sure their individual remote repository is up to date.

% source setup-ece2300.sh
% cd ${HOME}/ece2300/netid
% git pull
% tree

Where netid is your Cornell NetID. Now run all of the tests to ensure your design is fully functional.

% cd ${HOME}/ece2300/netid
% mkdir -p build
% cd build
% ../configure
% make check

We now need to get the files for your design from ecelinux onto the workstation. This requires multiple steps.

  • Step 1. Click Microsoft Edge on the desktop to open a web-browser on the workstation to log into GitHub and then find your repository

  • Step 2. Start PowerShell by clicking the Start menu then searching for Windows PowerShell

  • Step 3. Use the following command to change to your home directory on the workstation in the lab (where netid is your Cornell NetID)

% cd C:\Users\netid
  • Step 4. Clone your repo onto the workstation by using this command in PowerShell (where netid is your Cornell NetID, notice we are using https!):
% git clone https://github.com/cornell-ece2300/netid

  • Step 5. In the Connect to GitHub pop-up, click Sign in with your browser

  • Step 6. You may be asked for your GitHub username again and you may be asked to authorize the Git Credential Manager; click authorize git-ecosystem

  • Step 7. Verify that you have successfully cloned your repo by changing into your repo and using tree on the workstation:

% cd netid
% tree

Lab Check-Off Task 2: Verify Test Simulations, Discuss Optimizations

Show a TA that your hardware design is passing all test benches on ecelinux.

2. Setup Quartus Project

Click Quartus (Quartus Prime 18.1) on the desktop to start Quartus. Important: Ensure that the Quartus Version is 18.1 and not 23.1. Then, click Run the Quartus Prime software. You might need to try starting Quartus twice. Setup a new Quartus project using the New Project Wizard:

  • Directory, Name, Top-Level Entity
    • You must enter the working directory as follows with your NetID!
    • Working directory: C:\Users\netid\lab1
    • Name of this project: lab1
    • Name of top-level design entity: lab1
    • Click Next
  • Directory does not exist. Do you want to create it?
    • Click yes
  • Project Type
    • Choose Empty Project
    • Click Next
  • Add Files
    • Click triple dots to right of File name
    • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > netid > lab1 where netid is your Cornell NetID
    • Shift-click on every Verilog hardware design file (do not include any files in the test or sim subdirectories)
    • Click Open
    • The following steps are new; you did not do this in the primer!
    • Click User Libraries...
    • Click triple dots to the right of Project library name
    • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > netid where netid is your Cornell NetID
    • Click Select Folder
    • Click Add
    • Click OK
    • Click Next
  • Family, Device, and Board Settings
    • Click Board tab
    • Family: Cyclone V
    • Select DE0-CV Development Board
    • Make sure Create top-level design file is checked
    • Click Next
  • EDA Tool Settings
    • Click Next
  • Summary
    • Click Finish

3. Integrate, Synthesize, Analyze Unoptimized Five-Bit Numeric Display

We will start by integrating, synthesizing, and analyzing the unoptimized version of your five-bit numeric display. Refer back to the FPGA development primer for more details on each step.

3.1. Integrate

Start by spending a few minutes identifying the location of the input switches and the seven-segment displays on the board.

The ten switches are numbered from right to left. Switch SW[0] is the right-most switch, and switch SW[9] is the left-most switch. The seven-segment displays are also numbered from right to levet. Seven-segment display HEX0 is the right-most display, and seven-segment display HEX5 is the left-most display.

The New Project Wizard creates a top-level Verilog module for us which has ports for all of the switches, LEDs, seven-segment displays, and pins on the FPGA development board. You need to instantiate whatever design you want to synthesize and analyze in this top-level Verilog module and connect the ports appropriately.

  • Double-click on DE0_CV_golden_top
  • Instantiate DisplayUnopt_GL in the top-level module
  • Connect the ports as shown below
  • Choose File > Save from the menu
DisplayUnopt_GL display
(
  .in       (SW[4:0]),
  .seg_tens (HEX1),
  .seg_ones (HEX0)
);

Lab Check-Off Task 3: Explain Top-Level Connections

Show a TA the location of switches SW[0] through SW[4] on the board. Show the TA the location of seven-segment displays HEX0 and HEX1 on the board. Show the TA your top-level connections in Verilog, and clearly explain how the inputs and outputs of your DisplayUnopt_GL Verilog module will be hooked up to the physical switches and seven-segment displays on the board. Explain to the TA what is the expected behavior (i.e., when we flip these switches, we expect this to happen).

3.2. Synthesize and Analyze

Before we synthesize and analyze the unoptimized display unit, we need to create a timing constraint file. It is critical to understand that the FPGA tools do not synthesize the design to just run as fast as possible. The way the FPGA tools work, is that the designer provides a timing constraint on the critical path delay, and the tools work as hard as they can (but no harder!) to meet this critical path delay constraint. When finished, the design will either "meet timing" (i.e., the actual critical path delay is less than the constraint) or "not meet timing" (i.e., the actual critical path delay is greater than the contraint).

Here are the steps to create a timing constraint file:

  • Choose File > New from the menu
  • Click Synopsys Design Constraints File
  • Click OK
  • Enter the constraints shown below
  • Click File > Save from the menu
  • Name the file timing.sdc
  • Save the file in the lab1 directory

We will use the following initial constraints:

set_max_delay -from [all_inputs] -to [all_outputs] 20
set_min_delay -from [all_inputs] -to [all_outputs] 0

These constraints tell the FPGA tools that our critical path delay constraint is 20ns and that the FPGA tools should analyze all paths from every input port to every output port.

Now use the following steps to synthesize your design.

  • Choose Processing > Start Compilation from the menu
  • Wait 30-60 seconds for synthesis to complete

How do I fix "can't open Verilog Design File" errors?

This probably means you did not setup the user library correctly, so Quartus cannot find the files you are including using the include Verilog preprocessor directive. We did not need to setup the user library in the FPGA primer. You can use the following steps to fix this:

  • Choose Assignments > Settings from the menu
  • Select the category Libraries
  • Click triple dots to the right of Project library name
  • Click on This PC, then navigate to your cloned repo by choosing Windows (C:) > Users > netid > netid where netid is your Cornell NetID
  • Click Select Folder
  • Click Add
  • Click OK
  • Choose Processing > Start Compilation from the menu to see if this fixes the issue

Now let's look at the RTL viewer, technology map viewer, and chip planner.

  • RTL Viewer
    • Choose Tools > Netlist Viewer > RTL Viewer from the menu
    • Click + for a new tab
    • In Netlist Navigator choose DE0_CV_golden_top > Instances > DisplayUnopt_GL
    • Drag DisplayUnopt_GL into the empty tab
    • Double click on the green box to see in side DisplayUnopt_GL
    • Double click on the green box for BinaryToSevenSegUnopt_GL to see inside
    • Choose File > Close from menu to close the RTL viewer
  • Technology Map Viewer
    • Choose Tools > Netlist Viewer > Technology Map Viewer (Post-Fitting)
    • Click + for a new tab
    • In Netlist Navigator choose DE0_CV_golden_top > Instances > DisplayUnopt_GL
    • Drag DisplayUnopt_GL into the empty tab
    • Double click on the green box to see in side DisplayUnopt_GL
    • Double click on the green box for BinaryToSevenSegUnopt_GL to see inside
    • Choose File > Close from the menu to close the technology map viewer
  • Chip Planner
    • Choose Tools > Chip Planner from the menu
    • Identify where the logic used to implement your design is located in the FPGA
    • Choose File > Close from the menu to close the chip planner

Lab Report Task 1: Save RTL Viewer for Unoptimized Design

Save a screenshot of the RTL viewer for just BinaryToSevenSegUnopt_GL for your lab report. Press the Fn + Print Screen key to save a screenshot to the clipboard, then paste the screenshot into a Google Doc and crop appropriately for your lab report.

The next step is to analyze the area of your design.

  • Choose Processing -> Compilation Report from the menu. Under Table of Contents choose Fitter > Resource Section > Resource Usage Summary
  • Look through the report to determine the number of combinational ALUTs (configurable look-up tables) are used for your design

The final step is to analyze the timing (i.e., the critical path delay) of your design. We will analyze timing for the Slow 1100mV 85C Model which is the default choice in the Timing Analyzer.

  • Choose Tools > Timing Analyzer from the menu
  • Double-click Update Timing Netlist
  • Choose Reports > Custom Reports > Report Timing from the menu
  • Report Timing
    • From: [get_keepers SW*]
    • To: [get_keepers HEX*]
    • Report number of paths: 100
    • Click Report Timing
  • Identify the propagation delay of the longest path
  • Look at the actual critical path (i.e., Data Arrival Path) which shows the longest path from one of the input switches through your design to one of the seven-segment displays
  • Choose File > Close from the menu to close the timing analyzer

Lab Report Task 2: Save Critical Path for Unoptimized Design

Save a screenshot of just the critical path of your unoptimized design for your lab report. Press the Fn + Print Screen key to save a screenshot to the clipboard, then paste the screenshot into a Google Doc and crop appropriately for your lab report. The screenshot should clearly show the total delay, incremental delay, location, and element for each gate along the critical path. Make sure to include the "Elements" column so you can know what each row corresponds to in the path.

Lab Check-Off Task 4: Discuss RTL Viewer and Critical Path for Unoptimized Design

Show a TA your screenshot of the RTL viewer for just BinaryToSevenSegUnopt_GL and the corresponding Verilog side-by-side. Explain how the RTL viewer connects back to the Verilog for your design. Show a TA your screenshot of the critical path. Explain how the critical path connects back to the Verilog code for your design (i.e., where does the critical path start and end? what modules does the critical path go through?). Explain what is the actual delay of every single gate in the real FPGA along the critical path. What kind of delay model (i.e., a zero-delay model? a constant-delay model? a more complex delay model?) are the FPGA tools using to analyze the delay?

3.3. Iterate

Your design will almost certainly meet timing with a critical path delay constraint of 20ns. We are interested in the limit on the critical path delay (i.e., what is the true minimum critical path delay) so we can compare our unoptimized and optimized designs. To find the limit, we need to iteratively reduce the critical path timing constraint until we no longer meet timing. We can consider the shortest critical path delay while still meeting timing as the "true minimum critical path delay".

You can iteratively reduce the critical path delay, by changing 20 in the timing constraint file to something smaller. So the iterative process will look like this:

  • Edit the timing constraints file to reduce the critical path delay constraint
  • Choose Processing > Start Compilation from the menu
  • Wait 30-60 seconds for synthesis to complete
  • Analyze the area of your design
  • Analyze the timing of your design

You will be working to fill in this table:

Make a copy of this table, and enter in the data for your unoptimized design with a 20ns critical path delay constraint. You can find the number of 7-input ALUts, 6-input ALUts, etc in the area report. The critical path delay is just the Data Delay of the slowest path in the timing report.

Then iteratively reduce the timing constraint until your design no longer meets timing. We recommend trying 15ns and then iteratively decreasing the timing constraint by one nanosecond at a time. The "true minimum critical path delay" is the shortest critical path across all experiments that meets timing.

Lab Report Task 3: Collect Data for Unoptimized Design

Save your completed data table with your analysis of the unoptimized design and include it in your report's appendix.

Lab Check-Off Task 5: Discuss Area and Delay Analysis for Unoptimized Design

Show a TA your completed data table with your analysis of the unoptimized design. Explain if the number ALUTs (i.e., configurable truth tables) either does or does not match your expectation given your Verilog code. Discuss what you found for the "true minimum critical path delay" of your unoptimized design.

4. Integrate, Synthesize, Analyze Optimized Five-Bit Numeric Display

Now we will integrate, synthesize, and analyze the optimized version of your five-bit numeric display. Refer back to the FPGA development primer for more details on each step.

4.1. Integrate

We will not create a new project, but we will instead simply change which module is being instantiated in the top-level Verilog module provided for us by the New Project Wizard.

  • Double-click on DE0_CV_golden_top
  • Instantiate DisplayOpt_GL in the top-level module
  • Connect the ports as shown below
  • Choose File > Save from the menu
DisplayOpt_GL display
(
  .in       (SW[4:0]),
  .seg_tens (HEX1),
  .seg_ones (HEX0)
);

4.2. Synthesize and Analyze

We will repeat the steps we did to synthesize and analyze the unoptimized design, except now for the optimized design. Start by resetting the timing constraint file to use a 20ns critical path delay constraint:

set_max_delay -from [all_inputs] -to [all_outputs] 20
set_min_delay -from [all_inputs] -to [all_outputs] 0

Now use the following steps to synthesize your design and then look at the RTL viewer, technology map viewer, and chip planner.

  • Choose Processing > Start Compilation from the menu
  • Wait 30-60 seconds for synthesis to complete
  • RTL Viewer
    • Choose Tools > Netlist Viewer > RTL Viewer from the menu
    • Click + for a new tab
    • In Netlist Navigator choose DE0_CV_golden_top > Instances > DisplayOpt_GL
    • Drag DisplayOpt_GL into the empty tab
    • Double click on the green box to see in side DisplayOpt_GL
    • Double click on the green box for BinaryToSevenSegOpt_GL to see inside
    • Choose File > Close from menu to close the RTL viewer
  • Technology Map Viewer
    • Choose Tools > Netlist Viewer > Technology Map Viewer (Post-Fitting)
    • Click + for a new tab
    • In Netlist Navigator choose DE0_CV_golden_top > Instances > DisplayOpt_GL
    • Drag DisplayOpt_GL into the empty tab
    • Double click on the green box to see in side DisplayOpt_GL
    • Double click on the green box for BinaryToSevenSegOpt_GL to see inside
    • Choose File > Close from the menu to close the technology map viewer
  • Chip Planner
    • Choose Tools > Chip Planner from the menu
    • Identify where the logic used to implement your design is located in the FPGA
    • Choose File > Close from the menu to close the chip planner

Lab Report Task 4: Save RTL Viewer for Optimized Design

Save a screenshot of the RTL viewer for just BinaryToSevenSegOpt_GL for your lab report. Press the Fn + Print Screen key to save a screenshot to the clipboard, then paste the screenshot into a Google Doc and crop appropriately for your lab report.

The next step is to analyze the area of your design.

  • In Table of Contents choose Fitter > Resource Section > Resource Usage Summary
  • Look through the report to determine the number of combinational ALUTs (configurable look-up tables) are used for your design
  • How does this compare to your unoptimized design?

The final step is to analyze the timing (i.e., the critical path delay) of your design. Once again, we analyze the timing for the Slow 1100mV 85C Model which is the default choice in the Timing Analyzer.

  • Choose Tools > Timing Analyzer from the menu
  • Double-click Update Timing Netlist
  • Choose Reports > Custom Reports > Report Timing from the menu
  • Report Timing
    • From: [get_keepers SW*]
    • To: [get_keepers HEX*]
    • Report number of paths: 100
    • Click Report Timing
  • Identify the propagation delay of the longest path
  • Look at the actual critical path (i.e., Data Arrival Path) which shows the longest path from one of the input switches through your design to one of the seven-segment displays
  • How does this compare to your unoptimized design?
  • Choose File > Close from the menu to close the timing analyzer

Lab Report Task 5: Save Critical Path for Optimized Design

Save a screenshot of just the critical path of your optimized design for your lab report. Press the Fn + Print Screen key to save a screenshot to the clipboard, then paste the screenshot into a Google Doc and crop appropriately for your lab report. The screenshot should clearly show the total delay, incremental delay, location, and element for each gate along the critical path. Make sure to include the "Elements" column so you can know what each row corresponds to in the path.

4.3. Iterate

We are beginning to be able to compare our unoptmized and optimized designs, but need to find the "true minimum critical path delay" of the optimized design for a rigorous comparison. As with the unoptimized design, you can iteratively reduce the critical path delay, by changing 20 in the timing constraint file to smaller values one nanosecond at a time. The iterative process looks like this:

  • Edit the timing constraints file to reduce the critical path delay constraint by one nanosecond
  • Choose Processing > Start Compilation from the menu
  • Wait 30-60 seconds for synthesis to complete
  • Analyze the area of your design
  • Analyze the timing of your design

You will be working to fill out the rest of this table:

Work on the same copy of this table you made earlier, and enter in the data for your optimized design with a 20ns critical path delay constraint. Then iteratively reduce the timing constraint until your design no longer meets timing. We recommend trying 15ns and then iteratively decreasing the timing constraint by one nanosecond at a time. The "true minimum critical path delay" is the shortest critical path across all experiments that meets timing.

Lab Report Task 6: Collect Data for Optimized Design

Save your completed data table with your analysis of the optimized design and include it in your report's appendix.

Lab Check-Off Task 6: Discuss Optimized Design

The TA will ask one student how they optimized one of the outputs for the binary-to-seven-segment converter, and they will then ask the other student how they optimized a different output. Use your Karnaugh map to explain your optimization. Compare the gates required in your Verilog code to implement this output in the unoptimized vs optimized implementations. Show a TA your screenshot of the RTL viewer for both BinaryToSevenSegUnopt_GL and BinaryToSevenSegOpt_GL side-by-side. Are you able to see a difference? Show a TA your completed data table with your analysis of the optimized design. Discuss in detail your findings comparing the unoptimized vs. optimized implementations. What conclusions can we draw in terms of how much effort we should spend trying to optimize a gate-level implementation in our Verilog hardware designs?

5. Configure Five-Bit Numeric Display FPGA Prototype

We now have a fully verified Verilog hardware design, and we have finished a rigorous comparative analysis of the area and timing for both an unoptimized and optimized implementation. The last step is to configure the FPGA with our optimized design and demostrate the final FPGA prototype!

  • Choose Tools > Programmer from the menu
  • Click Hardware Setup
  • Currently selected hardware: USB-Blaster [USB-0]
  • Click Close
  • Click Start

Additionally, on ecelinux, go ahead and build and run the display interactive simulator.

% cd ${HOME}/ece2300/netid/build
% make display-sim
% ./display-sim +switches=00010
% ./display-sim +switches=00101

where as always netid is your NetID. Try out your display simulator for a few values and make sure that the FPGA behaves identically.

Lab Check-Off Task 7: Demonstrate the Five-Bit Numeric Display

First, show a TA the display interactive simulator. The TA will give you a decimal number. One student should first determine the binary representation, then use the interactive simulator to verify that your display correctly outputs the decimal representation. Then use the FPGA prototype to confirm it also outputs the correct decimal representation. The TA will give you a second decimal number to try, and now the second student should go through the same steps.

Lab Check-Off Task 8: Turn In FPGA Board

When you are finished with your demo, pack up your FPGA development board. Neatly put the board, power cable, and USB cable back in the box. Return the box to a TA who will then record the board number on your check-off sheet, initial the final check-off, and then collect your check-off sheet.